Abstract: A method includes forming a deep well region of a first conductivity type in a substrate, implanting a portion of the deep well region to form a first gate, and implanting the deep well region to form a well region. The well region and the first gate are of a second conductivity type opposite the first conductivity type. An implantation is performed to form a channel region of the first conductivity type over the first gate. A portion of the deep well region overlying the channel region is implanted to form a second gate of the second conductivity type. A source/drain implantation is performed to form a source region and a drain region of the first conductivity type on opposite sides of the second gate. The source and drain regions are connected to the channel region, and overlap the channel region and the first gate.

Abstract: A method includes forming a deep well region of a first conductivity type in a substrate, implanting a portion of the deep well region to form a first gate, and implanting the deep well region to form a well region. The well region and the first gate are of a second conductivity type opposite the first conductivity type. An implantation is performed to form a channel region of the first conductivity type over the first gate. A portion of the deep well region overlying the channel region is implanted to form a second gate of the second conductivity type. A source/drain implantation is performed to form a source region and a drain region of the first conductivity type on opposite sides of the second gate. The source and drain regions are connected to the channel region, and overlap the channel region and the first gate.

Abstract: A method includes forming a deep well region of a first conductivity type in a substrate, implanting a portion of the deep well region to form a first gate, and implanting the deep well region to form a well region. The well region and the first gate are of a second conductivity type opposite the first conductivity type. An implantation is performed to form a channel region of the first conductivity type over the first gate. A portion of the deep well region overlying the channel region is implanted to form a second gate of the second conductivity type. A source/drain implantation is performed to form a source region and a drain region of the first conductivity type on opposite sides of the second gate. The source and drain regions are connected to the channel region, and overlap the channel region and the first gate.

Abstract: An assembly includes a wafer having a top wafer surface and a wafer circumference. The assembly further includes a device arrangement structure. The device arrangement structure includes a first surface having a perimeter, the perimeter being encircled by the wafer circumference in a plan view; and an array of devices, each device of the array of devices having an electrical contact on the first surface. The assembly further includes an adhesive element configured to affix the device arrangement structure in a stationary position relative to the wafer, wherein the adhesive element includes a tape layer having an adhesive surface attached to the top surface of the device arrangement structure and attached to a surface of the wafer.

Abstract: An assembly includes a wafer having a top wafer surface and a wafer circumference. The assembly further includes a device arrangement structure. The device arrangement structure includes a first surface having a perimeter, the perimeter being encircled by the wafer circumference in a plan view; and an array of devices, each device of the array of devices having an electrical contact on the first surface. The assembly further includes an adhesive element configured to affix the device arrangement structure in a stationary position relative to the wafer, wherein the adhesive element includes a tape layer having an adhesive surface attached to the top surface of the device arrangement structure and attached to a surface of the wafer.

Abstract: An assembly includes a wafer having a top wafer surface and a wafer circumference and a device arrangement structure. The device arrangement structure includes a first surface having a perimeter, the perimeter being encircled by the wafer circumference in a plan view. The device arrangement structure also includes an array of devices, each device of the array of devices having an electrical contact on the first surface. The assembly has an adhesive element that affixes the device arrangement structure in a stationary position relative to the wafer.

Abstract: A method includes forming a deep well region of a first conductivity type in a substrate, implanting a portion of the deep well region to form a first gate, and implanting the deep well region to form a well region. The well region and the first gate are of a second conductivity type opposite the first conductivity type. An implantation is performed to form a channel region of the first conductivity type over the first gate. A portion of the deep well region overlying the channel region is implanted to form a second gate of the second conductivity type. A source/drain implantation is performed to form a source region and a drain region of the first conductivity type on opposite sides of the second gate. The source and drain regions are connected to the channel region, and overlap the channel region and the first gate.

Abstract: A semiconductor device includes a first die having a first active surface and a first backside surface opposite the first active surface, a second die having a second active surface and a second backside surface opposite the second active surface, and an interposer, the first active surface of the first die being electrically coupled to a first side of the interposer, the second active surface of the second die being electrically coupled to a second side of the interposer. The semiconductor device also includes a first connector over the interposer, a first encapsulating material surrounding the second die, the first encapsulating material having a first surface over the interposer, and a via electrically coupling the first connector and the interposer. A first end of the via is substantially coplanar with the first surface of the first encapsulating material.

Abstract: A method includes forming a deep well region of a first conductivity type in a substrate, implanting a portion of the deep well region to form a first gate, and implanting the deep well region to form a well region. The well region and the first gate are of a second conductivity type opposite the first conductivity type. An implantation is performed to form a channel region of the first conductivity type over the first gate. A portion of the deep well region overlying the channel region is implanted to form a second gate of the second conductivity type. A source/drain implantation is performed to form a source region and a drain region of the first conductivity type on opposite sides of the second gate. The source and drain regions are connected to the channel region, and overlap the channel region and the first gate.

Abstract: An assembly includes a wafer having a top wafer surface and a wafer circumference and a device arrangement structure. The device arrangement structure includes a first surface having a perimeter, the perimeter being encircled by the wafer circumference in a plan view. The device arrangement structure also includes an array of devices, each device of the array of devices having an electrical contact on the first surface. The assembly has an adhesive element that affixes the device arrangement structure in a stationary position relative to the wafer.

Abstract: An integrated circuit includes a digital-to-analog converter (DAC) circuit including at least one first channel type digital-to-analog converter (DAC) and at least one second channel type DAC. The integrated circuit further includes a plurality of sample and hold (S/H) circuits, each of the plurality of S/H circuits being coupled with a single DAC of the DAC circuit. A number of the at least one first channel type DAC is different than a number of the at least one second channel type DAC.

Abstract: Provided is a wafer level packaging. The packaging includes a first semiconductor wafer having a transistor device and a first bonding layer that includes a first material. The packaging includes a second semiconductor wafer having a second bonding layer that includes a second material different from the first material, one of the first and second materials being aluminum-based, and the other thereof being titanium-based. Wherein a portion of the second wafer is diffusively bonded to the first wafer through the first and second bonding layers.

Abstract: A two-stage digital-to-analog converter for outputting an analog voltage in response to a M-bit digital input code includes a two-bit serial charge redistribution digital-to-analog converter having a high reference voltage input node for receiving a high reference voltage and a low reference voltage input node for receiving a low reference voltage, and a voltage selector. The voltage selector sets the high reference voltage and low reference voltage to selected levels depending on at least a portion of the M-bit digital input code.

Abstract: An integrated circuit device includes a lightly doped region such as the base region of a bipolar junction transistor within a semiconductor body. The device further includes a UV barrier layer formed over the lightly doped region. The UV barrier protects the lightly doped region from damage that can occur during high energy plasma etching or UV irradiation to erase EPROM.

Abstract: A semiconductor device includes a first die having a first active surface and a first backside surface opposite the first active surface, a second die having a second active surface and a second backside surface opposite the second active surface, and an interposer, the first active surface of the first die being electrically coupled to a first side of the interposer, the second active surface of the second die being electrically coupled to a second side of the interposer. The semiconductor device also includes a first connector over the interposer, a first encapsulating material surrounding the second die, the first encapsulating material having a first surface over the interposer, and a via electrically coupling the first connector and the interposer. A first end of the via is substantially coplanar with the first surface of the first encapsulating material.

Abstract: An integrated circuit includes a digital-to-analog converter (DAC) circuit including at least one first channel type digital-to-analog converter (DAC) and at least one second channel type DAC. The integrated circuit further includes a plurality of sample and hold (S/H) circuits, each of the plurality of S/H circuits being coupled with a single DAC of the DAC circuit. A number of the at least one first channel type DAC is different than a number of the at least one second channel type DAC.

Abstract: An integrated circuit includes a digital-to-analog converter (DAC) circuit including at least one first channel type DAC and at least one second channel type DAC. The integrated circuit includes a plurality of sample and hold (S/H) circuits. Each of the S/H circuits is coupled with the DAC circuit. The S/H circuits are capable of receiving signals from the DAC circuit and outputting the signals in parallel.

Abstract: A semiconductor device includes a first die having a first active surface and a first backside surface opposite the first active surface, a second die having a second active surface and a second backside surface opposite the second active surface, and an interposer, the first active surface of the first die being electrically coupled to a first side of the interposer, the second active surface of the second die being electrically coupled to a second side of the interposer. The semiconductor device also includes a first connector over the interposer, a first encapsulating material surrounding the second die, the first encapsulating material having a first surface over the interposer, and a via electrically coupling the first connector and the interposer. A first end of the via is substantially coplanar with the first surface of the first encapsulating material.

Abstract: An integrated circuit device includes a lightly doped region such as the base region of a bipolar junction transistor within a semiconductor body. The device further includes a UV barrier layer formed over the lightly doped region. The UV barrier protects the lightly doped region from damage that can occur during high energy plasma etching or UV irradiation to erase EPROM.

Abstract: Provided is a wafer level packaging. The packaging includes a first semiconductor wafer having a transistor device and a first bonding layer that includes a first material. The packaging includes a second semiconductor wafer having a second bonding layer that includes a second material different from the first material, one of the first and second materials being aluminum-based, and the other thereof being titanium-based. Wherein a portion of the second wafer is diffusively bonded to the first wafer through the first and second bonding layers.