Patents by Inventor Minguk KANG

Minguk KANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240281924
    Abstract: Systems and methods for image processing are described. Embodiments of the present disclosure obtain a low-resolution image and a text description of the low-resolution image. A mapping network generates a style vector representing the text description of the low-resolution image. An adaptive convolution component generates an adaptive convolution filter based on the style vector. An image generation network generates a high-resolution image corresponding to the low-resolution image based on the adaptive convolution filter.
    Type: Application
    Filed: February 17, 2023
    Publication date: August 22, 2024
    Inventors: Taesung Park, Minguk Kang, Richard Zhang, Junyan Zhu, Elya Shechtman, Sylvain Paris
  • Publication number: 20240282025
    Abstract: Systems and methods for image generation are provided. An aspect of the systems and methods includes obtaining a text prompt, generating a style vector based on the text prompt, generating an adaptive convolution filter based on the style vector, and generating an image corresponding to the text prompt based on the adaptive convolution filter.
    Type: Application
    Filed: February 17, 2023
    Publication date: August 22, 2024
    Inventors: Taesung Park, Minguk Kang, Richard Zhang, Junyan Zhu, Elya Shechtman, Sylvain Paris
  • Patent number: 11437374
    Abstract: A semiconductor device includes a substrate including a logic cell region and a connection region, a dummy transistor on the connection region, an intermediate connection layer on the dummy transistor, a first metal layer on the intermediate connection layer, an etch stop layer between the intermediate connection layer and the first metal layer, a through contact below the first metal layer penetrating the connection region, an upper portion of the through contact protruding above the etch stop layer, and a protection insulating pattern on the etch stop layer covering the upper portion of the through contact. The protection insulating pattern covers an upper side surface of the through contact and a top surface of the through contact.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: September 6, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Shaofeng Ding, Minguk Kang, Jihyung Kim, Jeong Hoon Ahn, Haeri Yoo, Yun Ki Choi
  • Patent number: 11429777
    Abstract: A method of estimating warpage of an interposer and a method of manufacturing a semiconductor package by using the same are disclosed. The interposer includes a through electrode passing through a substrate, and a plurality of metal wiring layers and a plurality of insulating layers on the substrate, and the method of estimating warpage of an interposer includes: performing a temperature sweep test by using sample interposers, and measuring warpages according to temperatures; deriving a warpage slope, as a function of temperature, of each of the sample interposers; deriving a warpage model by linearly fitting the warpage slope with respect to an average pattern density of metal wiring layers in each of the sample interposers; and calculating a room temperature warpage reference value of the interposer based on the warpage model.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: August 30, 2022
    Inventors: Wonji Park, Jeonghoon Ahn, Jihyung Kim, Jaehee Oh, Yunki Choi, Minguk Kang
  • Publication number: 20220035984
    Abstract: A method of estimating warpage of an interposer and a method of manufacturing a semiconductor package by using the same are disclosed. The interposer includes a through electrode passing through a substrate, and a plurality of metal wiring layers and a plurality of insulating layers on the substrate, and the method of estimating warpage of an interposer includes: performing a temperature sweep test by using sample interposers, and measuring warpages according to temperatures; deriving a warpage slope, as a function of temperature, of each of the sample interposers; deriving a warpage model by linearly fitting the warpage slope with respect to an average pattern density of metal wiring layers in each of the sample interposers; and calculating a room temperature warpage reference value of the interposer based on the warpage model.
    Type: Application
    Filed: March 26, 2021
    Publication date: February 3, 2022
    Inventors: Wonji Park, Jeonghoon Ahn, Jihyung Kim, Jaehee Oh, Yunki Choi, Minguk Kang
  • Publication number: 20210242203
    Abstract: A semiconductor device includes a substrate including a logic cell region and a connection region, a dummy transistor on the connection region, an intermediate connection layer on the dummy transistor, a first metal layer on the intermediate connection layer, an etch stop layer between the intermediate connection layer and the first metal layer, a through contact below the first metal layer penetrating the connection region, an upper portion of the through contact protruding above the etch stop layer, and a protection insulating pattern on the etch stop layer covering the upper portion of the through contact. The protection insulating pattern covers an upper side surface of the through contact and a top surface of the through contact.
    Type: Application
    Filed: September 28, 2020
    Publication date: August 5, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Shaofeng DING, Minguk KANG, Jihyung KIM, Jeong Hoon AHN, Haeri YOO, Yun Ki CHOI