Abstract: A flash memory device including a high voltage generator circuit that is adapted to supply a program voltage having a target voltage to a selected word line is provided. The flash memory device is adapted to terminate the program interval in accordance with when the program voltage has been restored to the target voltage after dropping below the target voltage. A method for operating the flash memory device is also provided.

Abstract: A method is provided for verifying a programming operation of a flash memory device. The flash memory device includes at least one memory string in which a string selection transistor, multiple memory cells and a ground selection transistor are connected in series, and the programming operation is performed with respect to a selected memory cell in the memory string. The method includes applying a voltage, obtained by adding a threshold voltage of the string selection transistor to a power supply voltage, to a string selection line connected to the string selection transistor; applying a ground voltage to wordlines connected to each of the memory cells and a ground selection line connected to the ground selection transistor; precharging a bitline connected to the memory string to the power supply voltage; and determining whether a programming operation of the selected memory cell is complete.

Abstract: A flash memory device comprising a high voltage generator circuit that is adapted to supply a program voltage having a target voltage to a selected word line is provided. The flash memory device is adapted to terminate the program interval in accordance with when the program voltage has been restored to the target voltage after dropping below the target voltage. A method for operating the flash memory device is also provided.

Abstract: A flash memory device comprising a high voltage generator circuit that is adapted to supply a program voltage having a target voltage to a selected word line is provided. The flash memory device is adapted to terminate the program interval in accordance with when the program voltage has been restored to the target voltage after dropping below the target voltage. A method for operating the flash memory device is also provided.

Abstract: A method is provided for verifying a programming operation of a flash memory device. The flash memory device includes at least one memory string in which a string selection transistor, multiple memory cells and a ground selection transistor are connected in series, and the programming operation is performed with respect to a selected memory cell in the memory string. The method includes applying a voltage, obtained by adding a threshold voltage of the string selection transistor to a power supply voltage, to a string selection line connected to the string selection transistor; applying a ground voltage to wordlines connected to each of the memory cells and a ground selection line connected to the ground selection transistor; precharging a bitline connected to the memory string to the power supply voltage; and determining whether a programming operation of the selected memory cell is complete.

Abstract: In a nonvolatile memory device, a first verification result indicates whether a block of memory cells has been successfully programmed and a second verification result indicates whether a far cell in the block has been is successfully programmed. A controller defines the level and application time for the program voltage applied during a next program loop in response to the first and second verification results.

Abstract: A flash memory data storage apparatus comprises a flash memory and a flash interface. The flash memory transceives data through a flash bus group. The flash interface includes first through n'th flash input buffers that transfer data to a host bus group in stages in response to first through n'th transfer clock control signals. An i'th flash input buffer provides data through i'th input-buffer bus groups in number of at least Ni. A bus width of each of the i'th input-buffer bus groups is wider than a bus width of each of an (i?l)'th input-buffer bus groups. A period of an i'th transfer clock control signal is longer than a period of an (i?1)'th transfer clock control signal. The Ni is obtained by dividing a bus width of the flash bus group by dividing the bus width of the flash bus group by the bus width of the each of the i'th input-buffer bus groups.

Abstract: Some embodiments of the present invention provide programming operations for reducing a program time for a nonvolatile memory device. A nonvolatile semiconductor memory device is programmed by receiving data to be programmed into memory cells from a host, programming the data into the memory cells, performing a verify read operation to determine whether the data has been successfully programmed into the memory cells, and performing a Y-scan operation while performing the verify read operation to sequentially scan and output data read from bit lines coupled to the memory cells.

Abstract: A non-volatile memory device performs a multi-page copyback operation where after a plurality of copyback data read out from one or more mats are sequentially stored in a plurality of buffers, the stored data are simultaneously programmed to different mats. The copyback data may be read out without limitation to the location of mats and the number of copyback data to be read out from the respective mats. The read-out copyback data are simultaneously programmed to a plurality of mats.

Abstract: In a nonvolatile memory device, a first verification result indicates whether a block of memory cells has been successfully programmed and a second verification result indicates whether a far cell in the block has been is successfully programmed. A controller defines the level and application time for the program voltage applied during a next program loop in response to the first and second verification results.

Abstract: Some embodiments of the present invention provide programming operations for reducing a program time for a nonvolatile memory device. A nonvolatile semiconductor memory device is programmed by receiving data to be programmed into memory cells from a host, programming the data into the memory cells, performing a verify read operation to determine whether the data has been successfully programmed into the memory cells, and performing a Y-scan operation while performing the verify read operation to sequentially scan and output data read from bit lines coupled to the memory cells.

Abstract: A flash memory system capable of inputting/outputting data in units of sectors at random. The flash memory system includes a flash memory (a cell array), a buffer memory, a random data input/output circuit, and a control circuit. The random data input/output circuit receives data in units of sectors from the buffer memory or outputs the data in units of sectors to the buffer memory. The control circuit controls the order and the number of times of inputting/outputting data between the buffer memory and the random data input/output circuit.

Abstract: A flash memory device comprising a high voltage generator circuit that is adapted to supply a program voltage having a target voltage to a selected word line is provided. The flash memory device is adapted to terminate the program interval in accordance with when the program voltage has been restored to the target voltage after dropping below the target voltage. A method for operating the flash memory device is also provided.

Abstract: A non-volatile memory device performs a multi-page copyback operation where after a plurality of copyback data read out from one or more mats are sequentially stored in a plurality of buffers, the stored data are simultaneously programmed to different mats. The copyback data may be read out without limitation to the location of mats and the number of copyback data to be read out from the respective mats. The read-out copyback data are simultaneously programmed to a plurality of mats.

Abstract: In a flash memory data storage apparatus, a multistage flash input buffer unit is embedded in which data bus width is gradually extended and the period of a control clock is gradually made longer. In one example, the flash memory data storage apparatus renders its embedded flash memory to be accessed with 128-bit data in parallel in a period of 80 ns, while communicating with an external system for 16-bit data in parallel during a period of 20 ns. The flash memory data storage apparatus improves a data rate between the flash memory and a buffer memory, resulting in remarkable advancement of the data rate between the flash memory and an external system.

Abstract: A NAND-type flash memory device including a memory cell array having a plurality of memory blocks is provided.

Abstract: A flash memory system capable of inputting/outputting data in units of sectors at random. The flash memory system includes a flash memory (a cell array), a buffer memory, a random data input/output circuit, and a control circuit. The random data input/output circuit receives data in units of sectors from the buffer memory or outputs the data in units of sectors to the buffer memory. The control circuit controls the order and the number of times of inputting/outputting data between the buffer memory and the random data input/output circuit.

Abstract: A NAND-type flash memory device including a memory cell array having a plurality of memory blocks is provided.