Abstract: A pixel herein includes a color panel, a light emitting diode (LED) panel, and an adhesive layer disposed between the color panel and the LED panel. The color panel includes a transparent layer, a plurality of sub-pixel isolation structures, and a plurality of black matrix structures disposed between the plurality of sub-pixel isolation structures and the transparent layer. The sub-pixel isolation structures define a plurality color conversion wells of plurality of sub-pixels. A color conversion material is disposed in the color conversion well. The plurality of black matrix structures define a plurality of color resist wells of the plurality of sub-pixels. A color resist is disposed in the color resist wells. The LED panel includes a plurality of micro-LEDs disposed on a backplane. The plurality of micro-LEDs correspond to a sub-pixel.

Abstract: Embodiments of the present disclosure generally relate to LED pixels and methods of fabricating LED pixels. A device includes a backplane, at least three LEDs disposed on the backplane, subpixel isolation (SI) structures disposed defining wells of at least three subpixels, a reflection material is disposed on sidewalls and a top surface of the SI structures, at least three of the subpixels have a color conversion material disposed in the wells, an encapsulation layer disposed over the subpixel isolation structures and the subpixels, a light filter layer disposed over the encapsulation layer and micro-lenses disposed over the light filter layer and over each of the wells of the subpixels.

Abstract: A photocurable composition includes a blue photoluminescent material, one or more monomers, and a photoinitiator that initiates polymerization of the one or more monomers in response to absorption of the ultraviolet light. The blue photoluminescent material is selected to absorb ultraviolet light with a maximum wavelength in a range of about 300 nm to about 430 nm and to emit blue light. The blue photoluminescent material also has an emission peak in a range of about 420 nm to about 480 nm. The full width at half maximum of the emission peak is less than 100 nm, and the photoluminescence quantum yield is in a range of 5% to 100%.

Abstract: Processing methods are described that include forming a group of LED structures on a substrate layer to form a patterned LED substrate. The methods also include depositing a light absorption material on the pattered LED substrate, where the light absorption material includes at least one photocurable compound and at least one ultraviolet light absorbing material. The methods further include exposing a portion of the light absorption material to patterned light, wherein the patterned light cures the exposed portion of the light absorption material into pixel isolation structures. The methods additionally include depositing an isotropic layer on a top portion and a side portion of the pixel isolation structures, where the LED structures are substantially free of the as-deposited isotropic light reflecting layer.

Abstract: A display screen includes a backplane, an array of light-emitting diodes electrically integrated with the backplane, the array of light-emitting diodes configured to emit UV light in a first wavelength range, and a plurality of isolation walls formed on the backplane between adjacent light-emitting diodes of the array of light-emitting diodes with the isolation walls spaced apart from the light-emitting diodes and extending above the light-emitting diodes. The plurality of isolation walls include a core of a first material and a coating covering at least a portion of the core extending above the light-emitting diodes. The coating is an opaque second material having transmittance less than 1% of light in the first wavelength range.

Abstract: Any one of a plurality of to-be-grouped devices in a power supply system reports an initial bus voltage to a topology detection device; and reports a current bus voltage after delivering a bus voltage adjustment instruction to a target reference device. The bus voltage adjustment instruction instructs the target reference device to adjust a voltage. The target reference device receives the bus voltage adjustment instruction and adjusts the voltage according to the bus voltage adjustment instruction. The topology detection device obtains the initial bus voltage and the current bus voltage of the plurality of to-be-grouped devices, and determines, based on a difference between the initial bus voltage of the plurality of to-be-grouped devices and the current bus voltage of the plurality of to-be-grouped devices, whether the target reference device and a target to-be-grouped device are connected to a same bus.

Abstract: A method and system for implementing L3VPN based on a two-dimensional routing protocol. The method includes the following steps of: activating an L3VPN network to obtain a route destined to each user site; sending, by a user in a source user site, a packet to a user in a target user site, and sending the packet to an entry of a first edge routing device; performing encapsulation by the first edge routing device based on a public network IP address of the packet; and forwarding, by means of matching of two-dimensional routing, the encapsulated packet to an exit of the first edge routing device for decapsulation, and forwarding the same to the target user site via an entry of a second edge routing device.

Abstract: A method and system for implementing L3VPN based on a two-dimensional routing protocol. The method includes the following steps of: activating an L3VPN network to obtain a route destined to each user site; sending, by a user in a source user site, a packet to a user in a target user site, and sending the packet to an entry of a first edge routing device; performing encapsulation by the first edge routing device based on a public network IP address of the packet; and forwarding, by means of matching of two-dimensional routing, the encapsulated packet to an exit of the first edge routing device for decapsulation, and forwarding the same to the target user site via an entry of a second edge routing device.

Abstract: A system and method are disclosed for providing a self aligned bipolar transistor using a silicon nitride ring. An active region of the transistor is formed and a sacrificial emitter is formed above the active region of the transistor. A silicon nitride ring is formed around the sacrificial emitter. The sacrificial emitter and the silicon nitride ring are formed by depositing a layer of silicon nitride material over the active area of the transistor and performing an etch process to simultaneously create both the sacrificial emitter and the silicon nitride ring. The silicon nitride ring provides support for forming a raised external base for the transistor.

Abstract: A system and method are disclosed for providing a self aligned bipolar transistor using a simplified sacrificial nitride emitter. An active region of a transistor is formed and a silicon nitride sacrificial emitter is formed above the active region of the transistor. Then a physical vapor deposition oxide layer is deposited over the silicon nitride sacrificial emitter using a physical vapor deposition process. The physical vapor deposition oxide layer is then etched away from the side walls of the sacrificial emitter. The sacrificial emitter is then etched away to form an emitter window. Then a polysilicon emitter structure is formed in the emitter window. The self aligned bipolar transistor architecture of the invention is compatible with BiCMOS technology.

Abstract: A system and method are disclosed for providing a self aligned silicon germanium (SiGe) heterojunction bipolar transistor using a mesa emitter-base architecture. The transistor of the present invention comprises a non-selective epitaxial growth (NSEG) collector, an NSEG base, an NSEG emitter and a raised external base that is formed by the selective epitaxial growth (SEG) of a doped polysilicon layer.

Abstract: A system and method are disclosed for providing an improved polyemit module for a self aligned heterojunction bipolar transistor architecture. The polyemit module of the transistor of the present invention is formed using a double layer deposition process. In the double layer deposition process, the first layer is a layer of emitter polysilicon and the second layer is a sacrificial layer of silicon germanium (SiGe). The shape and thickness of the emitter polysilicon layer of the polyemit module provides (1) a reduction in the overall resistance of the emitter and (2) an increase in the contact area between the emitter polysilicon layer and a contact structure that is more than three times the contact area that is provided in prior art polyemit modules.

Abstract: A system and method are disclosed for providing a self aligned bipolar transistor using a sacrificial polysilicon external base. An active region of a transistor is formed and a sacrificial polysilicon external base is formed above the active region of the transistor and covered with a silicon oxide layer. Then an emitter window is etched and filled with silicon nitride. An etch procedure is subsequently performed to remove the sacrificial polysilicon external base. A layer of doped polysilicon material is then deposited to fill a cavity within the transistor formed by the removal of the sacrificial polysilicon external base. A polysilicon emitter structure is subsequently formed in the emitter window. The self aligned bipolar transistor architecture of the invention is compatible with BiCMOS technology.

Abstract: A system and method are disclosed for providing a fully self aligned bipolar transistor using modified cavity formation to optimize selective epitaxial growth. A collector of a transistor is formed and at least two layers of silicon oxide are formed above the collector and covered with a polysilicon external raised base. Then an emitter window is etched through the polysilicon external raised base down to the top layer of silicon oxide. A wet etch process is performed to form a cavity in the at least two layers of silicon oxide. Different wet etch rates of the silicon layers with respect to the wet etch process cause the cavity to be formed with a shape that optimizes selective epitaxial growth in the cavity. Polysilicon rich corners and a monocrystalline silicon base are then formed within the cavity.

Abstract: An x-ray tube (1) includes a heat shield (130) which intercepts heat radiating from an anode (10), thereby reducing the temperature of a bearing assembly (62). The heat shield includes outer and inner concentric cylinders (132, 134) spaced from each other by a vacuum gap (138). The heat shield and a stationary portion (114) of the bearing assembly are both connected to a cold plate (150) so that heat is not conducted from the cylinders to the bearing assembly but is instead carried away by the cold plate to the surrounding cooling oil.

Abstract: An x-ray tube (1) includes a heat shield (130) which intercepts heat radiating from an anode (10), thereby reducing the temperature of a bearing assembly (62). The heat shield includes outer and inner concentric cylinders (132, 134) spaced from each other by a vacuum gap (138). The heat shield and a stationary portion (114) of the bearing assembly are both connected to a cold plate (150) so that heat is not conducted from the cylinders to the bearing assembly but is instead carried away by the cold plate to the surrounding cooling oil.