Patents by Inventor Mingyang OU

Mingyang OU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for data synchronization between host side and FPGA accelerator
    Patent number: 11762790
    Abstract: Disclosed are a method for data synchronization between a host side and a Field Programmable Gate Array (FPGA) accelerator, a Bidirectional Memory Synchronize Engine (DMSE), a FPGA accelerator, and a data synchronization system. The method includes: in response to detection of data migration from a host side to a preset memory space, generating second state information according to first state information in a first address space, and writing the second state information to a second address space (S201); and in response to detection of the second state information in the second address space, calling Direct Memory Access (DMA) to migrate data in the preset memory space to a memory space of a FPGA accelerator, and copying the second state information to the first address space, so as to implement synchronization (S202).
    Type: Grant
    Filed: January 7, 2021
    Date of Patent: September 19, 2023
    Assignee: INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD.
    Inventors: Mingyang Ou, Jiaheng Fan, Hongwei Kan
  • METHOD FOR DATA SYNCHRONIZATION BETWEEN HOST SIDE AND FPGA ACCELERATOR
    Publication number: 20230098879
    Abstract: Disclosed are a method for data synchronization between a host side and a Field Programmable Gate Array (FPGA) accelerator, a Bidirectional Memory Synchronize Engine (DMSE), a FPGA accelerator, and a data synchronization system. The method includes: in response to detection of data migration from a host side to a preset memory space, generating second state information according to first state information in a first address space, and writing the second state information to a second address space (S201); and in response to detection of the second state information in the second address space, calling Direct Memory Access (DMA) to migrate data in the preset memory space to a memory space of a FPGA accelerator, and copying the second state information to the first address space, so as to implement synchronization (S202).
    Type: Application
    Filed: January 7, 2021
    Publication date: March 30, 2023
    Inventors: Mingyang OU, Jiaheng FAN, Hongwei KAN