Patents by Inventor Minh Q. Tran
Minh Q. Tran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9425325Abstract: The present claimed subject matter is directed to memory device that includes substrate, a tunneling layer over the substrate, a floating gate over the tunneling layer, a dielectric over the floating gate and including silicon oxynitride, and a control gate over the dielectric.Type: GrantFiled: January 13, 2014Date of Patent: August 23, 2016Assignee: CYPRESS SEMICONDUCTOR CORPORATIONInventors: Minh Q. Tran, Minh-Van Ngo, Alexander H. Nickel, Jeong-Uk Huh
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Patent number: 8735960Abstract: An ultraviolet light absorbent silicon oxynitride layer overlies a memory cell including a pair of source/drains, a gate insulator, a floating gate, a dielectric layer, and a control gate. A conductor is disposed through the silicon oxynitride layer for electrical connection to the control gate, and another conductor is disposed through the silicon oxynitride layer for electrical connection to a source/drain.Type: GrantFiled: November 17, 2008Date of Patent: May 27, 2014Assignee: Spansion LLCInventors: Minh Q. Tran, Minh-Van Ngo, Alexander H. Nickel, Sung Jin Kim, Simon Chan, Ning Cheng
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Publication number: 20140124848Abstract: The present claimed subject matter is directed to memory device that includes substrate, a tunneling layer over the substrate, a floating gate over the tunneling layer, a dielectric over the floating gate and including silicon oxynitride, and a control gate over the dielectric.Type: ApplicationFiled: January 13, 2014Publication date: May 8, 2014Applicant: SPANSION LLCInventors: Minh Q. TRAN, Minh-Van NGO, Alexander H. NICKEL, Jeong-Uk HUH
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Patent number: 8633074Abstract: The present memory device includes a substrate, a tunneling layer over the substrate, a floating gate over the tunneling layer, a dielectric over the floating gate and including silicon oxynitride, and a control gate over the dielectric. A method for fabricating such a memory device is also provided, including various approaches for forming the silicon oxynitride.Type: GrantFiled: September 17, 2008Date of Patent: January 21, 2014Assignee: Spansion LLCInventors: Minh Q. Tran, Minh-Van Ngo, Alexander H. Nickel, Jeong-Uk Huh
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Patent number: 8611035Abstract: A proximity sensor is described including a capacitor formed by a first conductive element and a second conductive element. The first conductive element and the second conductive element are situated at a magnetic head, a slider that connects to the magnetic head, a reader of the magnetic head, a writer of the magnetic head, a reader shield of the magnetic head, or a writer shield of the magnetic head. A capacitance and a fringing electric field are formed by the capacitor when there is a voltage difference between the first conductive element and the second conductive element. The capacitor is situated such that the fringing electric field changes with a positioning change of a magnetic storage medium with respect to at least one of the first conductive element and the second conductive element. The capacitor is also situated such that the capacitance changes with the fringing electric field change.Type: GrantFiled: February 6, 2012Date of Patent: December 17, 2013Assignee: Western Digital (Fremont), LLCInventors: Sateeshchandra S. Bajikar, Minh Q. Tran
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Patent number: 8026169Abstract: Data retention in flash memory devices, such as mirrorbit devices, is improved by reducing the generation and/or diffusion of hydrogen ions during back end processing, such as annealing inlaid Cu. Embodiments include annealing inlaid Cu in an N2 atmosphere containing low H2 or no H2, and at temperatures less than 200° C., e.g., 100° C. to 150° C.Type: GrantFiled: November 6, 2006Date of Patent: September 27, 2011Assignee: Advanced Micro Devices, Inc.Inventors: Lu You, Alexander Nickel, Minh Q. Tran, Minh-Van Ngo, Hieu Pham, Erik Wilson, Hirokazu Tokuno, Amir Hossein Jafarpour, Inkuk Kang, Robert Huertas
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Publication number: 20100123178Abstract: An ultraviolet light absorbent silicon oxynitride layer overlies a memory cell including a pair of source/drains, a gate insulator, a floating gate, a dielectric layer, and a control gate. A conductor is disposed through the silicon oxynitride layer for electrical connection to the control gate, and another conductor is disposed through the silicon oxynitride layer for electrical connection to a source/drain.Type: ApplicationFiled: November 17, 2008Publication date: May 20, 2010Inventors: Minh Q. Tran, Minh-Van Ngo, Alexander H. Nickel, Sung Jin Kim, Simon Chan, Ning Cheng
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Publication number: 20100065901Abstract: The present memory device includes a substrate, a tunneling layer over the substrate, a floating gate over the tunneling layer, a dielectric over the floating gate and including silicon oxynitride, and a control gate over the dielectric. A method for fabricating such a memory device is also provided, including various approaches for forming the silicon oxynitride.Type: ApplicationFiled: September 17, 2008Publication date: March 18, 2010Inventors: Minh Q. Tran, Minh-Van Ngo, Alexander H. Nickel, Jeong-Uk Huh
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Publication number: 20080108193Abstract: Data retention in flash memory devices, such as mirrorbit devices, is improved by reducing the generation and/or diffusion of hydrogen ions during back end processing, such as annealing inlaid Cu. Embodiments include annealing inlaid Cu in an N2 atmosphere containing low H2 or no H2, and at temperatures less than 200° C., e.g., 100° C. to 150° C.Type: ApplicationFiled: November 6, 2006Publication date: May 8, 2008Inventors: Lu You, Alexander Nickel, Minh Q. Tran, Minh-Van Ngo, Hieu Pham, Erik Wilson, Hirokazu Tokuno, Amir Hossein Jafarpour, Inkuk Kang, Robert Huertas
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Patent number: 7169706Abstract: An exemplary embodiment is related to a method of using an adhesion precursor in an integrated circuit fabrication process. The method includes providing a gas of material over a dielectric material and providing a copper layer over an adhesion precursor layer. The adhesion precursor layer is formed by the gas, and the dielectric material includes an aperture.Type: GrantFiled: October 16, 2003Date of Patent: January 30, 2007Assignee: Advanced Micro Devices, Inc.Inventors: Sergey D. Lopatin, Paul R. Besser, Alline F. Myers, Jeremias D. Romero, Minh Q. Tran, Lu You, Pin-Chin Connie Wang
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Patent number: 6998337Abstract: Semiconductor devices with highly reliable Cu interconnects exhibiting reduced resistance are formed by sequentially depositing a seed layer by PVD, depositing a conformal seed layer enhancement film by electroplating, and then thermal annealing the seed layer enhancement film in an inert or reducing atmosphere to expel impurities, enhance film conductivity, reduce film stress, increase film density, and reduce film roughness. Embodiments include single and dual Cu damascene techniques formed in dielectric layers having a dielectric constant no greater than about 3.9.Type: GrantFiled: December 8, 2003Date of Patent: February 14, 2006Assignee: Advanced Micro Devices, Inc.Inventor: Minh Q. Tran
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Patent number: 6992004Abstract: A method for manufacturing an integrated circuit having improved electromigration characteristics includes forming an aperture in an interlevel dielectric layer and providing a barrier layer in the aperture. The aperture is filled with a metal material and a barrier layer is provided above the metal material. An intermetallic region can be formed at an interface of the metal material and the barrier layer. The intermetallic material can be formed by implantation of species.Type: GrantFiled: July 31, 2002Date of Patent: January 31, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Paul R. Besser, Matthew S. Buynoski, Minh Q. Tran, Pin-Chin Connie Wang, Lu You, Sergey D. Lopatin, Jeremias D. Romero
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Patent number: 6979642Abstract: A method of forming a conductive structure such as a copper conductive structure, line, or via is optimized for large grain growth and distribution of alloy elements. The alloy elements can reduce electromigration problems associated with the conductive structure. The conductive structure is self-annealed or first annealed in a low temperature process over a longer period of time. Another anneal is utilized to distribute alloy elements.Type: GrantFiled: July 28, 2003Date of Patent: December 27, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Matthew S. Buynoski, Connie Pin-Chin Wang, Paul R. Besser, Minh Q. Tran
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Patent number: 6664187Abstract: Semiconductor devices with highly reliable Cu interconnects exhibiting reduced resistance are formed by sequentially depositing a seedlayer by PVD, depositing a conformal seedlayer enhancement film by CVD, and then laser thermal annealing the seedlayer enhancement film in nitrogen to expel impurities, enhance film conductivity, reduce film stress, increase film density, and reduce film roughness. Embodiments include single and dual Cu damascene techniques formed in dielectric layers having a dielectric constant no greater than about 3.9.Type: GrantFiled: April 3, 2002Date of Patent: December 16, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Minh Van Ngo, Minh Q. Tran
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Patent number: 6589408Abstract: A non-planar target can be configured for use in a plasma vapor deposition (PVD) process in which ions bombard the non-planar target and cause alloy atoms present in the non-planar target to be knocked loose and form an alloy film layer. The target includes a top planar section having a first alloy concentration and a side annular section having a second alloy concentration. The side annular section has ends coupled to ends of the top planar section. The first alloy concentration and the second alloy concentration are different.Type: GrantFiled: March 27, 2002Date of Patent: July 8, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Pin-Chin Connie Wang, Paul R. Besser, Sergey D. Lopatin, Minh Q. Tran
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Patent number: 6518167Abstract: A method of forming a metal or metal nitride layer interface between a copper layer and a silicon nitride layer can include providing a metal organic gas or metal/metal nitride precursor over a copper layer, forming a metal or metal nitride layer from reactions between the metal organic gas or metal/metal nitride precursor and the copper layer, and depositing a silicon nitride layer over the metal or metal nitride layer and copper layer. The metal or metal nitride layer can provide a better interface adhesion between the silicon nitride layer and the copper layer. The metal layer can improve the interface between the copper layer and the silicon nitride layer, improving electromigration reliability and, thus, integrated circuit device performance.Type: GrantFiled: April 16, 2002Date of Patent: February 11, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Lu You, Matthew S. Buynoski, Paul R. Besser, Jeremias D. Romero, Pin-Chin Connie Wang, Minh Q. Tran
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Publication number: 20020106905Abstract: A method for removing copper from the edge of a semiconductor wafer to prevent particle and copper contamination provides a photoresist or other protective layer on top of the copper. An edge bead removal process is performed on the photoresist to expose the edge of the copper on the semiconductor wafer. An etchant that is selective to the copper and does not attack photoresist material is applied to the semiconductor wafer. The edge of the copper, which forms the potential source of particle or copper contamination, is thereby etched. The remaining copper, protected by the photoresist layer, remains unexposed to the etchant. After the copper edge has been removed, the photoresist material is also removed to expose the protected underlying copper for further processing.Type: ApplicationFiled: February 7, 2001Publication date: August 8, 2002Applicant: Advanced Micro Devices, Inc.Inventors: Minh Q. Tran, Richard J. Huang
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Patent number: 4926094Abstract: This invention relates to a high-performance gyrotron for the production of electromagnetic millimeter or submillimeter waves with a quasi-optical resonator. The latter is formed by two concave mirrors (1, 2) placed mutually opposite one another on an optical axis. For increasing the decoupling efficiency as well as for reducing the radiation into the environment the quasi-optical resonator is placed in a housing (4), which at least in sections is electrically conductive.Type: GrantFiled: March 1, 1988Date of Patent: May 15, 1990Assignee: Centre for Recherches En Physique Des PlasmasInventors: Anders Bondeson, Bernhard Isaak, Andre Perrenoud, Minh Q. Tran
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Patent number: 4705988Abstract: A device for guiding an electron beam from an electron gun to a microwave resonator in a microwave source operating according to the gyrotron principle, including a beam duct for guiding the electron beam, wherein the beam duct encloses the electron beam and has an electrically highly conductive surface area. For damping unwanted wave modes inside the beam duct, a plurality of damping openings are provided in the surface area of the beam duct. The characteristic aperture size (a) of the damping openings is larger than the wavelength of the modes to be damped. A particularly simple implementation employs wire mesh with an appropriate mesh size used as the material for the surface area of the beam duct.Type: GrantFiled: September 9, 1985Date of Patent: November 10, 1987Assignee: Centre de Recherches en Physique des Plasma (CRPP)Inventors: Minh Q. Tran, Anders Bondeson