Abstract: A method for forming a single damascene and/or dual damascene, contact and interconnect structure, comprising: performing front end processing, depositing copper including a copper barrier, annealing the copper in at least 90% N2 with less than 10% H2, performing planarization, performing in-situ low-H NH3 plasma treatment and low Si—H SiN etch stop layer deposition, and performing remaining back end processing.

Abstract: A method for forming a single damascene and/or dual damascene, contact and interconnect structure, comprising: performing front end processing, depositing copper including a copper barrier, annealing the copper in at least 90% N2 with less than 10% H2, performing planarization, performing in-situ low-H NH3 plasma treatment and low Si—H SiN etch stop layer deposition, and performing remaining back end processing.

Abstract: An integrated circuit is provided including forming a porous ultra-low dielectric constant dielectric layer over a semiconductor substrate and forming an opening in the ultra-low dielectric constant dielectric layer. A dielectric liner is formed to line the opening to cover the pores in the ultra-low dielectric constant dielectric layer and a barrier layer is deposited to line the dielectric liner and conductor core is deposited to fill the opening over the barrier layer.

Abstract: Barrier metal layer discontinuities or gaps due to low-k dielectric porosity is reduced by sealing sidewall porosity before barrier metal layer deposition. Embodiments include sealing sidewall porosity by depositing a swelling agent, adhesion promoter or an additional layer of low-k material.

Abstract: An interconnect structure is formed with a plurality of layers of a conductive material with a grain boundary between any two adjacent layers of the conductive material. Such grain boundaries between layers of conductive material act as shunt by-pass paths for migration of atoms of the conductive material to minimize migration of atoms of the conductive material along the interface between a dielectric passivation or capping layer and the interconnect structure. When the interconnect structure is a via structure, each of the layers of the conductive material and each of the grain boundary are formed to be perpendicular to a direction of current flow through the via structure. Such grain boundaries formed between the plurality of layers of conductive material in the via structure minimize charge carrier wind-force along the direction of current flow through the via structure to further minimize electromigration failure of the via structure.

Abstract: For forming a dual damascene opening within a dielectric material, a via mask material and a trench mask material are formed over the dielectric material. A trench opening is formed through the trench mask material, and a via opening is formed through a via mask patterning material disposed over the via and trench mask materials. The via and trench mask materials exposed through the via opening of the via mask patterning material are etched away, and the via mask patterning material is etched away. A portion of the dielectric material exposed through the via opening is etched down to the underlying interconnect structure, and a portion of the dielectric material exposed through the trench opening is etched, to form the dual damascene opening.

Abstract: The present invention provides an alloy electroplating system for semiconductor wafers including a plating chamber connected by a circulating system to a plating solution reservoir. The semiconductor wafer is used as the cathode with an inert primary anode in the plating chamber. A plurality of consumable remote secondary anodes at different voltages in the plating solution reservoir provides the metal ions for alloy plating.

Abstract: The present invention provides a method and system for polishing a wafer surface. The method and system comprises determining whether a thickness of the wafer surface is uniform while the wafer surface is being polished, and adjusting the polishing process while the wafer surface is being polished based on the determination of whether the thickness of the wafer surface is uniform. Through the use of the method and system in accordance with the present invention, in-situ adjustments can be made to the CMP polishing process while the wafer is actually being polished. This results in a substantial improvement in polishing uniformity.

Abstract: A manufacturing method for an integrated circuit is provided having a semiconductor substrate with a semiconductor device. A dielectric layer is on the semiconductor substrate and has an opening provided therein. An amorphized barrier layer lines the opening and a seed layer is deposited to line the amorphized barrier layer. A conductor core fills the opening over the barrier layer to form a conductor channel. The seed layer is securely bonded to the amorphized barrier layer and prevents electromigration along the surface between the seed and barrier layers.

Abstract: A manufacturing method is provided for an integrated circuit having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening. A conductor core with a random grain texture fills the opening over the barrier layer. The crystallographic orientation of the conductor core is then graphoepitaxially changed to reduce its random grain texture.

Abstract: A method is provided for X-ray imaging and analyzing grain boundaries, nodules or extrusions, voids, and separations or delaminations in conductive layers under dielectric capping layers in integrated circuit interconnects.

Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A dielectric layer is on the semiconductor substrate and has an opening provided therein. A barrier layer lines the opening. An amorphized layer is formed by rapid heating of the barrier layer and rapid cooling of the semiconductor substrate. A seed layer is deposited to line the amorphized barrier layer. A conductor core fills the opening over the barrier layer to form a conductor channel. The seed layer is securely bonded to the amorphized barrier layer.

Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A dielectric layer is on the semiconductor substrate and has an opening provided therein. A barrier layer lines the opening and has a first amorphized atomic layer of a barrier compound and a second atomic layer of a barrier metal. A seed layer is deposited to line the amorphized barrier layer. A conductor core fills the opening over the barrier layer to form a conductor channel. The seed layer is securely bonded to the amorphized barrier layer and prevents electromigration along the surface between the seed and barrier layers.

Abstract: A manufacturing method for an integrated circuit is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening. A seed layer is deposited over the barrier layer. The seed and barrier layers are then removed above the channel dielectric layer. A second seed layer is deposited over the semiconductor substrate. A conductor layer is electroplated over the second seed layer to fill the opening. The electroplated conductor layer and the second seed layer are removed above the channel dielectric layer.

Abstract: An electroplating system is provided for seed layer covered semiconductor wafers. A plating chamber is provided with an inert primary anode connectible to a positive voltage source and a semiconductor wafer connector connectible to a negative voltage source. The plating chamber further contains a consumable ring secondary anode connectible to the positive voltage source such that, when the plating chamber is filled with a plating solution and a semiconductor wafer is connected to the semiconductor wafer connector and the voltages are connected, the seed layer on the semiconductor wafer will be plated by consuming the consumable ring secondary anode.

Abstract: The present invention provides an electroplating system for semiconductor wafers including a plating chamber connected by a circulating system to a plating solution reservoir. The semiconductor wafer is used as the cathode with an inert primary anode in the plating chamber. A consumable remote secondary anode in the plating solution reservoir provides the metal ions for plating.

Abstract: An electroplating system is provided for semiconductor wafers which include a plating chamber having a consumable shielded secondary anode shielded by an inert anode from a semiconductor wafer connector. For a copper plating system the plating chamber has a consumable copper shielded anode shielded by an inert platinum anode from a semiconductor wafer connector.

Abstract: A manufacturing method for an integrated circuit is provided having a semiconductor substrate with a semiconductor device. A dielectric layer is on the semiconductor substrate and has an opening provided therein. An amorphized barrier layer lines the opening and a seed layer is deposited to line the amorphized barrier layer. A conductor core fills the opening over the barrier layer to form a conductor channel. The seed layer is securely bonded to the amorphized barrier layer and prevents electromigration along the surface between the seed and barrier layers.

Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A dielectric layer is on the semiconductor substrate and has an opening provided therein. An amorphized barrier layer lines the opening and a seed layer is deposited to line the amorphized barrier layer. A conductor core fills the opening over the barrier layer to form a conductor channel. The seed layer is securely bonded to the amorphized barrier layer and prevents electromigration along the surface between the seed and barrier layers.