Abstract: A thermal cut-off device includes a plastic base, two electrodes, a temperature sensing element, and a plastic cover that fits over the base. The temperature sensing element is curved downward, and may be a bimetal or a trimetal. When the device is subject to an over-temperature condition, the orientation of the curve flips such that the temperature sensing element is then curved upward. When the temperature sensing element is curved upward, it lifts an arm of one of the electrodes, which severs the electrical connection between the electrodes. In this manner the device shuts off during an over-temperature condition in order to protect the circuit in which the device is installed. To prevent corrosion of the temperature sensing element, a first moisture insulation layer is applied to the outer surface of the thermal cut-off device. The moisture insulation layer may be an epoxy adhesive or a UV/visible light-cured adhesive or light/heat cured adhesive.

Abstract: A method of manufacturing a surface mount device includes providing at least one core device and at least one lead frame. The core device is attached to the lead frame. The core device and the lead frame are encapsulated within an encapsulant. The encapsulant comprises a liquid epoxy that when cured has an oxygen permeability of less than approximately 0.4 cm3·mm/m2·atm·day.

Abstract: A method of manufacturing a surface mount device includes forming a plaque from a material, forming a plurality of conductive protrusions on a top surface and a bottom surface of the plaque, and applying a liquid encapsulant over at least a portion of the top surface and at least a portion of the bottom surface of the plaque. The liquid encapsulant is cured and when cured encapsulant has an oxygen permeability of less than about 0.4 cm3·mm/m2·atm·day. The assembly is cut to provide a plurality of components. After cutting, the top surface of each component includes at least one conductive protrusion, the bottom surface of each component includes at least one conductive protrusion, the top surface and the bottom surface of each component include the cured encapsulant, and a core of each component includes the material.

Abstract: A method of manufacturing a surface mount device includes providing at least one core device and at least one lead frame. The core device is attached to the lead frame. The core device and the lead frame are encapsulated within an encapsulant. The encapsulant comprises a liquid epoxy that when cured has an oxygen permeability of less than approximately 0.4 cm3•mm/m2•atm•day.

Abstract: A method of manufacturing a surface mount device includes forming a plaque from a material, forming a plurality of conductive protrusions on a top surface and a bottom surface of the plaque, and applying a liquid encapsulant over at least a portion of the top surface and at least a portion of the bottom surface of the plaque. The liquid encapsulant is cured and when cured encapsulant has an oxygen permeability of less than about 0.4 cm3·mm/m2·atm·day. The assembly is cut to provide a plurality of components. After cutting, the top surface of each component includes at least one conductive protrusion, the bottom surface of each component includes at least one conductive protrusion, the top surface and the bottom surface of each component include the cured encapsulant, and a core of each component includes the material.

Abstract: A thermal cut-off device includes a plastic base, two electrodes, a temperature sensing element, and a plastic cover that fits over the base. The temperature sensing element is curved downward, and may be a bimetal or a trimetal. When the device is subject to an over-temperature condition, the orientation of the curve flips such that the temperature sensing element is then curved upward. When the temperature sensing element is curved upward, it lifts an arm of one of the electrodes, which severs the electrical connection between the electrodes. In this manner the device shuts off during an over-temperature condition in order to protect the circuit in which the device is installed. To prevent corrosion of the temperature sensing element, a first moisture insulation layer is applied to the outer surface of the thermal cut-off device. The moisture insulation layer may be an epoxy adhesive or a UV/visible light-cured adhesive or light/heat cured adhesive.

Abstract: An exemplary embodiment relates to a method for forming a metal oxide semiconductor field effect transistor (MOSFET). The method includes providing a substrate having a gate formed above the substrate and performing at least one of the following depositing steps: depositing a spacer layer and forming a spacer around a gate and gate insulator located above a layer of silicon above the substrate; depositing an etch stop layer above the spacer, the gate, and the layer of silicon; and depositing a dielectric layer above the etch stop layer. At least one of the depositing a spacer layer, depositing an etch stop layer, and depositing a dielectric layer comprises high compression deposition which increases in tensile strain in the layer of silicon.

Abstract: A method of protecting a charge trapping dielectric flash memory cell from UV-induced charging, including fabricating a charge trapping dielectric flash memory cell including a charge trapping dielectric charge storage layer in a semiconductor device; and during processing steps subsequent to formation of the charge trapping dielectric charge storage layer, protecting the charge trapping dielectric flash memory cell from exposure to a level of UV radiation sufficient to deposit a non-erasable charge in the charge trapping dielectric flash memory cell. In one embodiment, the step of protecting is carried out by selecting processes in BEOL fabrication which do not include use, generation or exposure of the semiconductor device to a level of UV radiation sufficient to deposit the non-erasable charge.

Abstract: A method of protecting a SONOS flash memory cell from UV-induced charging, including fabricating a SONOS flash memory cell in a semiconductor device; and depositing over the SONOS flash memory cell at least one UV-protective layer, the UV-protective layer including a substantially UV-opaque material. In one embodiment, the device includes a substantially UV-opaque sub-layer of a contact cap layer or a substantially UV-opaque contact cap layer.

Abstract: Systems and methodologies are disclosed for increasing the number of memory cells associated with a lithographic feature. The systems comprise memory elements that are formed on the sidewalls of the lithographic feature by employing various depositing and etching processes. The side wall memory cells can have a bit line of the wafer as the first electrode and operate with a second formed electrode to activate a portion of an organic matter that is formed there between.

Abstract: An exemplary embodiment relates to a method for forming a metal oxide semiconductor field effect transistor (MOSFET). The method includes providing a substrate having a gate formed above the substrate and performing at least one of the following depositing steps: depositing a spacer layer and forming a spacer around a gate and gate insulator located above a layer of silicon above the substrate; depositing an etch stop layer above the spacer, the gate, and the layer of silicon; and depositing a dielectric layer above the etch stop layer. At least one of the depositing a spacer layer, depositing an etch stop layer, and depositing a dielectric layer comprises high compression deposition which increases in tensile strain in the layer of silicon.

Abstract: Systems and methods are disclosed for creating smooth surfaces for layers that are employed in memory cells and have previously been subject to a CMP process. The present invention employs various cycles of exposing the post CMP surface to inorganic and organic acids, as well as growing passive layers. The systems and methods may comprise an electroless feature for forming the passive layers.

Abstract: A method of performing decontamination of a chamber for use in an IC fabrication system includes providing wet oxygen or a mixture comprising hydrochloric gas and oxygen in the chamber and raising the temperature in the chamber from a first lower temperature to a second higher temperature to cause the wet oxygen or the mixture comprising hydrochloric gas and oxygen to react with the germanium.

Abstract: The formation of shallow trench isolations in a strained silicon MOSFET includes performing ion implantation in the strained silicon layer in the regions to be etched to form the trenches of the shallow trench isolations. The dosage of the implanted ions and the energy of implantation are chosen so as to damage the crystal lattice of the strained silicon throughout the thickness of the strained silicon layer in the shallow trench isolation regions to such a degree that the etch rate of the strained silicon in those regions is increased to approximately the same as or greater than the etch rate of the underlying undamaged silicon germanium. Subsequent etching yields trenches with significantly reduced or eliminated undercutting of the silicon germanium relative to the strained silicon. This in turn substantially prevents the formation of fully depleted silicon on insulator regions under the ends of the gate, thus improving the MOSFET leakage current.

Abstract: The formation of shallow trench isolations in a strained silicon MOSFET includes implantation of a dopant into overhang portions of the strained silicon layer and silicon germanium layer at the edges of trenches in which shallow trench isolations are to be formed. The conductivity type of the dopant is chosen to be opposite the conductivity type of the source and drain dopants. The implanted dopant increases the threshold voltage Vt beneath the ends of the gate in overhang portions of the strained silicon layer so that it is approximately equal to or greater than that of the remainder of the MOSFET. The resulting strained silicon MOSFET exhibits reduced leakage current beneath the ends of the gate.

Abstract: According to one exemplary embodiment, a structure comprises a substrate. The structure further comprises at least one memory cell situated on the substrate. The at least one memory cell may be, for example, a SONOS flash memory cell. The structure further comprises an interlayer dielectric layer situated over at least one memory cell and over the substrate. The structure further comprises a first antireflective coating layer situated over the interlayer dielectric layer. According to this exemplary embodiment, the structure further comprises a second antireflective coating layer situated directly over the first anti reflective coating layer. Either the first antireflective coating layer or second antireflective coating layer must be a silicon-rich layer. The first antireflective coating layer and the second antireflective coating may form a UV radiation blocking layer having a UV transparency less than approximately 1.0 percent, for example.

Abstract: A transistor architecture utilizes a raised source and drain region to reduce the adverse affects of germanium on silicide regions. Epitaxial growth can form a silicide region above the source and drain. The protocol can utilize any number of silicidation processes. The protocol allows better silicidation in SMOS devices.

Abstract: A fabrication system utilizes a protocol for removing germanium from a top surface of a wafer. An exposure to a gas, such as a gas containing the hydrochloric acid can remove germanium from the top surface. The protocol can allow shared equipment to be used in both Flash product fabrication lines and strained silicon (SMOS) fabrication lines. The protocol allows better silicidation in SMOS devices.

Abstract: According to one exemplary embodiment, a structure comprises a substrate. The structure further comprises at least one memory cell situated on the substrate. The at least one memory cell may be, for example, a flash memory cell, such as a SONOS flash memory cell and may include a gate situated over an ONO stack. The structure further comprises an interlayer dielectric layer situated over the at least one memory cell and over the substrate. According to this exemplary embodiment, the structure further comprises a UV radiation blocking layer situated directly over the interlayer dielectric layer, where the UV radiation blocking layer is selected from the group consisting of silicon-rich oxide and silicon-rich nitride. The UV radiation blocking layer may have a thickness of between approximately 1500.0 Angstroms and approximately 2000.0 Angstroms, for example.

Abstract: A method for filling an isolation trench structure during a semiconductor fabrication process is disclosed. The method includes a two-step deposition process that includes depositing a silicon-rich liner on the trench surface, and thereafter, filling the isolation trenches with an oxide utilizing a biased high density plasma deposition process. In a preferred embodiment, the silicon-rich liner is an in-situ HDP liner having a thickness of between 100 and 400 Angstroms, and preferably 200 Angstroms. Depositing a silicon-rich liner on the trench surface prior to depositing the high density plasma oxide eliminates the formation of defects at the surface of the isolation trench structure. Thus, the quality of the oxide fill is improved, as is yield and device performance.