Abstract: Integrated circuit transmission lines are designed to match elements at opposing ends of the transmission line over a frequency range of interest. By modifying characteristics of the transmission line over the length of the transmission line, from a first end coupled to a first external element to a second end coupled to a second external element, return loss is improved. In various embodiments one or more of the width of the conductors and the distance between adjacent edges of the conductors are modified across the length of the transmission line. In an alternative embodiment, the conductors of the transmission line are segmented with each segment having a length and a width across the segment.

Abstract: Integrated circuit transmission lines are designed to match elements at opposing ends of the transmission line over a frequency range of interest. By modifying characteristics of the transmission line over the length of the transmission line, from a first end coupled to a first external element to a second end coupled to a second external element, return loss is improved. In various embodiments one or more of the width of the conductors and the distance between adjacent edges of the conductors are modified across the length of the transmission line. In an alternative embodiment, the conductors of the transmission line are segmented with each segment having a length and a width across the segment.

Abstract: Systems, devices and methods are disclosed herein for reducing crosstalk between pairs of differential signal conductors. One or more ground traces connected to one or more over- or under-lying ground planes by vias are located between pairs of differential signal conductors. The electrical shielding provided by the combination of the one or more ground traces and the one or more ground planes results in reduced cross-talk between different pairs of differential signal conductors, and facilitates high-speed data rates between integrated circuits and printed circuit boards. In a preferred embodiment, such ground traces and ground planes are employed in HiTCE packaging containing multiple pairs of differential signal conductors.

Abstract: An apparatus for minimizing parasitic capacitance on a semiconductor die includes a semiconductor die having a least one signal line and at least one plane and an anti pad located between the at least one signal line and the at least one plane.

Abstract: Systems, devices and methods are disclosed herein for reducing crosstalk between pairs of differential signal conductors. One or more ground traces connected to one or more over- or under-lying ground planes by vias are located between pairs of differential signal conductors. The electrical shielding provided by the combination of the one or more ground traces and the one or more ground planes results in reduced cross-talk between different pairs of differential signal conductors, and facilitates high-speed data rates between integrated circuits and printed circuit boards. In a preferred embodiment, such ground traces and ground planes are employed in HiTCE packaging containing multiple pairs of differential signal conductors.

Abstract: A stripline structure. The stripline structure includes a stripline transmission line, a first ground plane, a first dielectric layer overlaying the first ground plane, a conductive trace overlaying the first dielectric layer, a second dielectric layer overlaying the conductive trace, a second ground plane overlaying the second dielectric layer, multiple first conductive vias, and multiple second conductive vias. Each first conductive via and each second conductive via electrically connects the first ground plane to the second ground plane. The multiple first conductive vias are located along a first line parallel to the conductive trace, and the multiple second conductive vias are located along a second line parallel to the conductive trace. The first line and the second line are located on opposite sides of the conductive trace.

Abstract: A stripline structure. The stripline structure includes a stripline transmission line, a first ground plane, a first dielectric layer overlaying the first ground plane, a conductive trace overlaying the first dielectric layer, a second dielectric layer overlaying the conductive trace, a second ground plane overlaying the second dielectric layer, multiple first conductive vias, and multiple second conductive vias. Each first conductive via and each second conductive via electrically connects the first ground plane to the second ground plane. The multiple first conductive vias are located along a first line parallel to the conductive trace, and the multiple second conductive vias are located along a second line parallel to the conductive trace. The first line and the second line are located on opposite sides of the conductive trace.