Patents by Inventor Minhan Chen

Minhan Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10326417
    Abstract: A resistor in a pair of resistors is selectively coupled to a current source through a selection switch during the reset phase of a voltage-mode sense amplifier so that one evaluation node for the voltage-mode sense amplifier is discharged from a power supply voltage by an ohmic voltage drop across the selectively-coupled resistor to null an offset for the voltage-mode sense amplifier.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: June 18, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Todd Morgan Rasmus, Minhan Chen
  • Publication number: 20190173440
    Abstract: A resistor in a pair of resistors is selectively coupled to a current source through a selection switch during the reset phase of a voltage-mode sense amplifier so that one evaluation node for the voltage-mode sense amplifier is discharged from a power supply voltage by an ohmic voltage drop across the selectively-coupled resistor to null an offset for the voltage-mode sense amplifier.
    Type: Application
    Filed: December 1, 2017
    Publication date: June 6, 2019
    Inventors: Todd Morgan Rasmus, Minhan Chen
  • Patent number: 10079698
    Abstract: Aspects of the disclosure are directed to determining an offset calibration step size of a sample latch. In accordance with one aspect, the disclosure relate to a Decision Feedback Equalizer (DFE) input section including a E sample latch to output a target signal sample; a E sample digital to analog converter coupled to the E sample latch to input a target voltage to the E sample latch; a sample latch to output a signal sample; and a voltage digital to analog converter coupled to the E sample latch and the sample latch to generate a bias voltage, wherein the bias voltage is inputted to the E sample latch and the sample latch. The DFE input section may further include a latch offset decoder to scale the bias voltage and a summing amplifier to receive an analog input waveform to the DFE input section.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: September 18, 2018
    Assignee: QUALCOMM Incorporated
    Inventor: Minhan Chen
  • Patent number: 9722823
    Abstract: Systems and methods for providing offset calibration for low power and high performance receivers are described herein. In one embodiment, a receiver comprises a sample latch having a first input coupled to a receive data path, and a second input. The receive also comprises a first digital-to-analog converter (DAC), a second DAC, and a calibration controller. In a calibration mode, the calibration controller is configured to input a calibration voltage to the first input of the sample latch using the first DAC, to input a threshold voltage and an offset-cancelation voltage to the second input of the sample latch using the second DAC, to adjust the offset-cancelation voltage, to observe an output of the sample latch as the offset-cancelation voltage is adjusted, and to store a value of the offset-cancelation voltage at which a metastable state is observed at the output of the sample latch in a memory.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: August 1, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Minhan Chen, Kenneth Luis Arcudia
  • Patent number: 9614502
    Abstract: A receiver according to one aspect comprises a latch configured to sample a data signal according to a sampling clock signal, and a plurality of offset-compensation segments, wherein each of the segments is coupled to an internal node of the latch. Each of the segments comprises a compensation transistor, and a step-adjustment transistor coupled in series with the compensation transistor. The receiver further comprises an offset controller configured to selectively turn on one or more of the compensations transistors to reduce an offset voltage of the latch, and a bias circuit configured to apply a bias voltage to a gate of each of one or more of the step-adjustment transistors.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: April 4, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Minhan Chen, Kenneth Luis Arcudia
  • Publication number: 20170040983
    Abstract: A receiver according to one aspect comprises a latch configured to sample a data signal according to a sampling clock signal, and a plurality of offset-compensation segments, wherein each of the segments is coupled to an internal node of the latch. Each of the segments comprises a compensation transistor, and a step-adjustment transistor coupled in series with the compensation transistor. The receiver further comprises an offset controller configured to selectively turn on one or more of the compensations transistors to reduce an offset voltage of the latch, and a bias circuit configured to apply a bias voltage to a gate of each of one or more of the step-adjustment transistors.
    Type: Application
    Filed: August 4, 2015
    Publication date: February 9, 2017
    Inventors: Minhan Chen, Kenneth Luis Arcudia
  • Publication number: 20160294583
    Abstract: Systems and methods for providing offset calibration for low power and high performance receivers are described herein. In one embodiment, a receiver comprises a sample latch having a first input coupled to a receive data path, and a second input. The receive also comprises a first digital-to-analog converter (DAC), a second DAC, and a calibration controller. In a calibration mode, the calibration controller is configured to input a calibration voltage to the first input of the sample latch using the first DAC, to input a threshold voltage and an offset-cancelation voltage to the second input of the sample latch using the second DAC, to adjust the offset-cancelation voltage, to observe an output of the sample latch as the offset-cancelation voltage is adjusted, and to store a value of the offset-cancelation voltage at which a metastable state is observed at the output of the sample latch in a memory.
    Type: Application
    Filed: June 7, 2016
    Publication date: October 6, 2016
    Inventors: Minhan Chen, Kenneth Luis Arcudia
  • Patent number: 9444657
    Abstract: Dynamically calibrating an offset of a receiver with a DFE while performing data transport operations, the DFE comprising a plurality of independent data transport banks, at least one data transport bank operating a data transport mode and at least one data transport bank operating in a calibration mode, including: iteratively, while carrying out data transport operations: utilizing the data transport bank operating in the data transport mode to perform data transport operations; calibrating the data transport bank operating in the calibration mode; and upon completing calibration of the data transport bank operating in the calibration mode, switching the mode of each data transport bank.
    Type: Grant
    Filed: July 10, 2013
    Date of Patent: September 13, 2016
    Assignee: International Business Machines Corporation
    Inventors: Minhan Chen, Jieming Qi
  • Publication number: 20160216317
    Abstract: In one embodiment, a method for operating a receiver having a first receiver input and a second receiver input is described herein. The method comprises receiving a data signal via the first and second receiver inputs in a mission mode, AC-coupling the received data signal to an amplifier, and amplifying the AC-coupled data signal using the amplifier. The method also comprises receiving one or more test signals via one or both of the first and second receiver inputs in a test mode, DC-coupling the received one or more test signals to a test receiver, and determining whether there are one or more defects based on the one or more test signals received by the test receiver.
    Type: Application
    Filed: January 22, 2015
    Publication date: July 28, 2016
    Inventors: Minhan Chen, Kenneth Luis Arcudia, Bupesh Pandita
  • Patent number: 9385695
    Abstract: Systems and methods for providing offset calibration for low power and high performance receivers are described herein. In one embodiment, a method for offset calibration comprises inputting a first voltage to a first input of a sample latch, and inputting a second voltage and an offset-cancellation voltage to a second input of the sample latch. The method also comprises adjusting the offset-cancellation voltage, observing an output of the sample latch as the offset-cancellation voltage is adjusted, and recording a value of the offset-cancellation voltage at which a metastable state is observed at the output of the sample latch. The method may be performed for each one of a plurality of different voltage levels for the first voltage to determine an offset-cancellation voltage for each one of the voltage levels.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: July 5, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Minhan Chen, Kenneth Luis Arcudia
  • Publication number: 20150358005
    Abstract: Systems and methods for providing offset calibration for low power and high performance receivers are described herein. In one embodiment, a method for offset calibration comprises inputting a first voltage to a first input of a sample latch, and inputting a second voltage and an offset-cancelation voltage to a second input of the sample latch. The method also comprises adjusting the offset-cancelation voltage, observing an output of the sample latch as the offset-cancelation voltage is adjusted, and recording a value of the offset-cancelation voltage at which a metastable state is observed at the output of the sample latch. The method may be performed for each one of a plurality of different voltage levels for the first voltage to determine an offset-cancelation voltage for each one of the voltage levels.
    Type: Application
    Filed: June 6, 2014
    Publication date: December 10, 2015
    Inventors: Minhan Chen, Kenneth Luis Arcudia
  • Patent number: 9209948
    Abstract: Testing a Decision Feedback Equalizer (‘DFE’), the DFE including a summing amplifier operatively coupled to a plurality of latches and an input signal line for receiving a data signal, including: preventing a differential data signal from being received by the summing amplifier; and iteratively for each tap to be tested: setting a tap coefficient for each tap to zero; setting an output of the plurality of latches to a predetermined value; setting a tap coefficient for the tap to be tested to a full scale value; and determining whether a resultant output signal from the DFE matches a predetermined expected output signal.
    Type: Grant
    Filed: January 19, 2015
    Date of Patent: December 8, 2015
    Assignee: International Business Machines Corporation
    Inventors: Eugene R. Atwood, Matthew B. Baecher, Minhan Chen, Hayden C. Cranford, Jr., William R. Kelly, Todd M. Rasmus
  • Patent number: 9184948
    Abstract: A Decision Feedback Equalizer (‘DFE’) that includes: a plurality of input signal lines comprising at least one data signal line and a plurality of power control signal lines; at least one output signal line; and a plurality of independently-controlled isolated power domains, where each independently-controlled isolated power domain is coupled to a corresponding one of the power control signal lines, each of the power control signal lines configured to transmit a power control signal to the independently-controlled isolated power domain dynamically, and each independently-controlled isolated power domain selectively consumes power in response to the power control signal, each independently-controlled isolated power domain configured to be dynamically powered up or powered down without impacting signal processing operations.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: November 10, 2015
    Assignee: GLOBALFOUNDRIES U.S. 2 LLC
    Inventors: Minhan Chen, Steven M. Clements, Carrie E. Cox, Todd M. Rasmus
  • Publication number: 20150131707
    Abstract: Testing a Decision Feedback Equalizer (‘DFE’), the DFE including a summing amplifier operatively coupled to a plurality of latches and an input signal line for receiving a data signal, including: preventing a differential data signal from being received by the summing amplifier; and iteratively for each tap to be tested: setting a tap coefficient for each tap to zero; setting an output of the plurality of latches to a predetermined value; setting a tap coefficient for the tap to be tested to a full scale value; and determining whether a resultant output signal from the DFE matches a predetermined expected output signal.
    Type: Application
    Filed: January 19, 2015
    Publication date: May 14, 2015
    Inventors: EUGENE R. ATWOOD, MATTHEW B. BAECHER, MINHAN CHEN, HAYDEN C. CRANFORD, JR., WILLIAM R. KELLY, TODD M. RASMUS
  • Patent number: 9014254
    Abstract: Testing a Decision Feedback Equalizer (‘DFE’), the DFE including a summing amplifier operatively coupled to a plurality of latches and an input signal line for receiving a data signal, including: preventing a differential data signal from being received by the summing amplifier; and iteratively for each tap to be tested: setting a tap coefficient for each tap to zero; setting an output of the plurality of latches to a predetermined value; setting a tap coefficient for the tap to be tested to a full scale value; and determining whether a resultant output signal from the DFE matches a predetermined expected output signal.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: April 21, 2015
    Assignee: International Business Machines Corporation
    Inventors: Eugene R. Atwood, Matthew B. Baecher, Minhan Chen, Hayden C. Cranford, Jr., William R. Kelly, Todd M. Rasmus
  • Publication number: 20150019770
    Abstract: Dynamically calibrating an offset of a receiver with a DFE while performing data transport operations, the DFE comprising a plurality of independent data transport banks, at least one data transport bank operating a data transport mode and at least one data transport bank operating in a calibration mode, including: iteratively, while carrying out data transport operations: utilizing the data transport bank operating in the data transport mode to perform data transport operations; calibrating the data transport bank operating in the calibration mode; and upon completing calibration of the data transport bank operating in the calibration mode, switching the mode of each data transport bank.
    Type: Application
    Filed: July 10, 2013
    Publication date: January 15, 2015
    Applicant: International Business Machines Corporation
    Inventors: Minhan Chen, Jieming Qi
  • Publication number: 20140376603
    Abstract: Testing a Decision Feedback Equalizer (‘DFE’), the DFE including a summing amplifier operatively coupled to a plurality of latches and an input signal line for receiving a data signal, including: preventing a differential data signal from being received by the summing amplifier; and iteratively for each tap to be tested: setting a tap coefficient for each tap to zero; setting an output of the plurality of latches to a predetermined value; setting a tap coefficient for the tap to be tested to a full scale value; and determining whether a resultant output signal from the DFE matches a predetermined expected output signal.
    Type: Application
    Filed: June 19, 2013
    Publication date: December 25, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: EUGENE R. ATWOOD, MATTHEW B. BAECHER, MINHAN CHEN, HAYDEN C. CRANFORD, Jr., WILLIAM R. KELLY, TODD M. RASMUS
  • Publication number: 20140355661
    Abstract: A Decision Feedback Equalizer (DFE) that includes: a plurality of input signal lines comprising at least one data signal line and a plurality of power control signal lines; at least one output signal line; and a plurality of independently-controlled isolated power domains, where each independently-controlled isolated power domain is coupled to a corresponding one of the power control signal lines, each of the power control signal lines configured to transmit a power control signal to the independently-controlled isolated power domain dynamically, and each independently-controlled isolated power domain selectively consumes power in response to the power control signal, each independently-controlled isolated power domain configured to be dynamically powered up or powered down without impacting signal processing operations.
    Type: Application
    Filed: May 28, 2013
    Publication date: December 4, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Minhan CHEN, Steven M. CLEMENTS, Carrie E. COX, Todd M. RASMUS
  • Patent number: 8798204
    Abstract: A serial link receiver comprises first and second input terminals for receiving positive and negative inputs of a serial data signal, first and second broadband matching T-coils coupled to the first and second input terminals, first and second AC/DC coupling networks coupled to the first and second broadband matching T-coils, and a common mode level shifter coupled to the outputs from the first and second AC/DC coupling networks. This receiver architecture combines the ability to have a wide bandwidth input and pass through data signals at both low and high frequencies. This AC and DC coupled front end also incorporates the feature of a common mode level shifting network to place the common mode of the signal at the optimum point for the first active amplifier stage.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: August 5, 2014
    Assignee: International Business Machines Corporation
    Inventors: Minhan Chen, Hayden C. Cranford, Jr.
  • Publication number: 20130064326
    Abstract: A serial link receiver comprises first and second input terminals for receiving positive and negative inputs of a serial data signal, first and second broadband matching T-coils coupled to the first and second input terminals, first and second AC/DC coupling networks coupled to the first and second broadband matching T-coils, and a common mode level shifter coupled to the outputs from the first and second AC/DC coupling networks. This receiver architecture combines the ability to have a wide bandwidth input and pass through data signals at both low and high frequencies. This AC and DC coupled front end also incorporates the feature of a common mode level shifting network to place the common mode of the signal at the optimum point for the first active amplifier stage.
    Type: Application
    Filed: September 9, 2011
    Publication date: March 14, 2013
    Applicant: International Business Machines Corporation
    Inventors: Minhan Chen, Hayden C. Cranford, JR.