Abstract: The semiconductor memory device including a bit line in a first direction on a substrate, a channel structure on the bit line, and including a first vertical part in a second direction, and a second vertical part apart from the first vertical part in the first direction and in the second direction, a back-gate electrode on the bit line on a side of the channel structure and in the second direction, a back-gate insulating film between the back-gate electrode and the channel structure, a back-gate capping film on the back-gate electrode and the back-gate insulating film, a first and second word lines between the first and the second vertical parts and in the second direction, the second word line spaced apart from the first word line in the first direction and first and second capacitors connected to the first and second vertical parts, on the first and second vertical parts.

Abstract: The inventive concept provides a substrate treating apparatus. The substrate treating apparatus includes discharging a treating liquid including a polymer and a solvent onto a substrate; and solidifying a liquid film of the treating liquid by volatilizing the solvent from the treating liquid on the substrate, and wherein the solidifying a liquid film comprises a first period of stopping the rotation of the substrate or rotating the substrate at a first speed for a first time period.

Abstract: A substrate treating method including removing particles formed on a substrate by continuously performing a process of supplying a treatment liquid including a polymer and a solvent onto the substrate, forming a solidified liquid film by volatilizing the solvent in the treatment liquid, removing the solidified liquid film from the substrate by supplying a stripping liquid onto the substrate, and supplying a rinse liquid onto the substrate may be provided.

Abstract: An AI-based automatic advertisement evaluation system includes a survey setup unit configured to model a global panel advertisement pre-evaluation item list, a survey information collection unit configured to collect global panel advertisement evaluation data for a survey list provided by the survey setup unit, an advertisement evaluation analysis unit configured to analyze the global panel advertisement evaluation data collected by the survey information collection unit based on AI, and an advertisement result display unit configured to visualize data analysis results of the advertisement evaluation analysis unit.

Abstract: A semiconductor memory device with improved performance by improving interface characteristics while reducing a leakage current, and a method for fabricating the same are provided. The semiconductor memory device includes a conductive line on a substrate, a first interlayer insulating layer exposing the conductive line and defining a channel trench on the substrate, a channel layer extending along a bottom and side surface of the channel trench, a first gate electrode and a second gate electrode spaced apart from each other in the channel trench, a first gate insulating layer between the channel layer and the first gate electrode, and a second gate insulating layer between the channel layer and the second gate electrode. The channel layer includes a first oxide semiconductor layer and a second oxide semiconductor layer sequentially stacked on the conductive line. The first oxide semiconductor layer has a greater crystallinity than the second oxide semiconductor layer.

Abstract: A semiconductor memory device with improved performance by improving interface characteristics while reducing a leakage current, and a method for fabricating the same are provided. The semiconductor memory device includes a conductive line on a substrate, a first interlayer insulating layer exposing the conductive line and defining a channel trench on the substrate, a channel layer extending along a bottom and side surface of the channel trench, a first gate electrode and a second gate electrode spaced apart from each other in the channel trench, a first gate insulating layer between the channel layer and the first gate electrode, and a second gate insulating layer between the channel layer and the second gate electrode. The channel layer includes a first oxide semiconductor layer and a second oxide semiconductor layer sequentially stacked on the conductive line. The first oxide semiconductor layer has a greater crystallinity than the second oxide semiconductor layer.

Abstract: A semiconductor memory includes a bit line extending in a first direction, first and second active patterns, which are alternately disposed in the first direction and on the bit line, and each of which includes a horizontal portion and a vertical portion, first word lines disposed on the horizontal portions of the first active patterns to cross the bit line, second word lines disposed on the horizontal portions of the second active patterns to cross the bit line, and an intermediate structure provided in a first gap region between the first and second word lines or in a second gap region between the vertical portions of the first and second active patterns. The first and second active patterns, which are adjacent to each other, may be disposed to be symmetric with respect to each other.

Abstract: A semiconductor device may include a bit line on the substrate, a channel pattern on the bit line and extending in a direction perpendicular to the bit line, a word line intersecting the bit line and spaced apart from the channel pattern, a gate insulating pattern between the channel pattern and the word line, an insulating pattern on the word line, and a landing pad connected to the channel pattern. The gate insulating pattern may include a first gate insulating pattern and a second gate insulating pattern having a first dielectric constant and a second dielectric constant, respectively. The second gate insulating pattern may be between the first gate insulating pattern and the word line. The first and second dielectric constants may be different. A first width of the first gate insulating pattern may be different from a second width of the second gate insulating pattern.

Abstract: A semiconductor device includes: a substrate; a bit line above the substrate; a channel pattern on the bit line extending in a direction perpendicular to an upper surface of the bit line; a word line intersecting the bit line and spaced apart from the channel pattern; a gate insulating pattern between the channel pattern and the word line; an insulating pattern on the word line; and a landing pad connected to the channel pattern. The channel pattern includes first, second, and third channel patterns that are sequentially stacked, the first channel pattern is connected to the bit line, the second channel pattern is between the first channel pattern and the third channel pattern, the third channel pattern is connected to the landing pad, the first channel pattern and the third channel pattern include a crystalline oxide semiconductor material, and the second channel pattern includes an amorphous oxide semiconductor material.

Abstract: A semiconductor memory device including: a stack structure including a plurality of layers that are vertically stacked on a substrate, each of the plurality of layers including a word line, a channel layer, and a data storage element electrically connected to the channel layer; and a bit line that vertically extends on one side of the stack structure, wherein the word line includes: a first conductive line that extends in a first direction; and a gate electrode that protrudes in a second direction from the first conductive line, the second direction intersecting the first direction, wherein the channel layer is on the gate electrode, and wherein the bit line includes a connection part electrically connected to the channel layer.

Abstract: A semiconductor device includes a bit line extending in a first direction on a substrate. A first insulating pattern is disposed on the bit line. A channel pattern is disposed on an upper side of the bit line and a lateral side of the first insulating pattern. The channel pattern includes an oxide semiconductor material. A gate insulating pattern is disposed on the channel pattern. Word lines are disposed on the gate insulating pattern. A second insulating pattern is disposed on the word lines. A landing pad is disposed on the channel pattern. An interlayer insulating layer disposed between the bit line and the channel pattern.

Abstract: Aspects of the present inventive concept provide a semiconductor device capable of enhancing performance and reliability through source/drain engineering in a transistor including an oxide semiconductor layer. The semiconductor device includes a substrate, a metal oxide layer disposed on the substrate, a source/drain pattern being in contact with the metal oxide layer and including a portion protruding from a top surface of the metal oxide layer, a plurality of gate structures disposed on the metal oxide layer with the source/drain pattern interposed therebetween and each including gate spacers and an insulating material layer, the insulating material layer being in contact with the metal oxide layer, and not extending along a top surface of the source/drain pattern, and a contact disposed on the source/drain pattern, the contact being connected to the source/drain pattern.

Abstract: The inventive concept provides a substrate treating apparatus which is cool a support plate having a heater faster than a conventional substrate treating apparatus. The substrate treating apparatus includes a housing providing a treating space therein; and a support unit configured to support a substrate at the treating space. The support unit includes a heater member provided at the support plate to heat the substrate and a cooling unit configured to cool the heater member. The cooling unit includes a first gas supply nozzle positioned under an edge of the heater member for supplying a cooling gas to a center direction of a bottom surface of the heater member and a second gas supply nozzle positioned under a center of the heater member for supplying the cooling gas in an edge direction of the bottom surface of the heater member.

Abstract: The inventive concept provides a substrate treating method. The substrate treating method includes supplying a dissolving solution onto a rotating substrate; and supplying, after the supplying a dissolution solution, a treating liquid including a polymer onto the rotating substrate to form a liquid film.

Abstract: A semiconductor memory device in which performance and reliability are improved, and a method for fabricating the same are provided. The semiconductor memory device includes a conductive line extending in a first direction on a substrate, an interlayer insulation film that includes a cell trench extending in a second direction intersecting the first direction, on the substrate, a first gate electrode and a second gate electrode that are spaced apart from each other in the first direction and each extend in the second direction, inside the cell trench, a channel layer that is inside the cell trench and is electrically connected to the conductive line, on the first gate electrode and the second gate electrode, and a gate insulation layer interposed between the first gate electrode and the channel layer, and between the second gate electrode and the channel layer.

Abstract: Disclosed is a memory device including a row decoder generating word line (WL) control signals based on a row address from an external device, a first sub-array including memory cells connected to word lines, a first sub-word line driver (SWD) providing a selection voltage or a non-selection voltage to odd-numbered word lines of the word lines based on odd-numbered WL control signals corresponding to the odd-numbered word lines, and a second SWD providing the selection voltage or the non-selection voltage to even-numbered word lines of the word lines based on even-numbered WL control signals corresponding to the even-numbered word lines. The first SWD applies the non-selection voltage to non-selection word lines of the even-numbered word lines, in response to the even-numbered WL control signals, and the second SWD applies the non-selection voltage to non-selection word lines of the odd-numbered word lines, in response to the odd-numbered WL control signals.

Abstract: A 3D semiconductor memory device includes a first through-structure on a substrate, the first through-structure comprising first and second conductive pillars spaced apart from each other in a first direction, an electrode adjacent to the first through-structure, the electrode horizontally extending in the first direction, and a ferroelectric layer and a channel layer between the electrode and the first and second conductive pillars. The channel layer connects the first and second conductive pillars to each other. The ferroelectric layer is disposed between the electrode and the channel layer. The ferroelectric layer extends from a sidewall of the first conductive pillar to a sidewall of the second conductive pillar along the channel layer when viewed in a plan view.

Abstract: The substrate processing apparatus of the present invention comprises a hot plate for heating a substrate; and a cooling unit for cooling the hot plate; wherein the cooling unit includes a support plate having a space formed between the support plate and the hot plate, and a plurality of nozzles installed on the support plate and for supplying cooling gas to a bottom surface of the hot plate, wherein an outdoor air inlet passage provided in a through structure is provide in the support plate, wherein a portion of the outdoor air inlet passage forms a first region, through which a cable passes, and the remaining portion forms a second region, through which the cable does not pass and outdoor air introduces.

Abstract: The inventive concept provides a substrate treating method. The substrate treating method includes supplying a dissolving solution onto a rotating substrate; and supplying, after the supplying a dissolution solution, a treating liquid including a polymer onto the rotating substrate to form a liquid film.

Abstract: A semiconductor device includes a first single crystal semiconductor pattern including a first source/drain region, a second source/drain region, and a first vertical channel region between the first source/drain region and the second source/drain region, the second source/drain region being at a higher level than the first source/drain region; a first gate electrode facing a first side surface of the first single crystal semiconductor pattern; a first gate dielectric layer, the first gate dielectric layer including a portion between the first single crystal semiconductor pattern and the first gate electrode; and a complementary structure in contact with a second side surface of the first single crystal semiconductor pattern, wherein the complementary structure includes an oxide semiconductor layer.