Abstract: A semiconductor device includes a channel layer located on a substrate, the channel layer including a conductive oxide, a gate structure located on the channel layer, the gate structure including a gate electrode and gate spacers located on both sidewalls of the gate electrode, and source and drain regions located on both sides of the gate structure in recess regions having a first height from a top surface of the channel layer. The source and drain regions are configured to apply tensile stress to a portion of the channel layer located under the gate structure.

Abstract: A semiconductor device includes a channel layer located on a substrate, the channel layer including a conductive oxide, a gate structure located on the channel layer, the gate structure including a gate electrode and gate spacers located on both sidewalls of the gate electrode, and source and drain regions located on both sides of the gate structure in recess regions having a first height from a top surface of the channel layer. The source and drain regions are configured to apply tensile stress to a portion of the channel layer located under the gate structure.

Abstract: A semiconductor device includes a device isolation region defining an active region in a substrate, and gate structures buried in the active region of the substrate. At least one of the gate structures includes a gate trench, a gate insulating layer conformally formed on an inner wall of the gate trench, a gate barrier pattern conformally formed on the gate insulating layer disposed on a lower portion of the gate trench, a gate electrode pattern formed on the gate barrier pattern and filling the lower portion of the gate trench, an electrode protection layer conformally formed on the gate insulating layer disposed on an upper portion of the gate trench to be in contact with the gate barrier pattern and the gate electrode pattern, a buffer oxide layer conformally formed on the electrode protection layer, and a gate capping insulating layer formed on the buffer oxide layer to fill the upper portion of the gate trench.

Abstract: An apparatus and method for retransmission in a wireless communication system. The method includes transmitting data to a Mobile Station (MS), identifying if there is an error in the transmitted data through a control message, if there occurs an error in the data, allocating resources for retransmitting data for erroneous data, transmitting information on the resources allocated for retransmission, to the MS, and retransmitting the data for the erroneous data to the MS.

Abstract: A method for transmitting and receiving signals using multiple frequency band in a wireless communication system are provided, in which a BS determines whether an MS is to use a plurality of FAs, selects the plurality of FAs if it is determined that the MS is to use the plurality of FAs, transmits FA information about the selected FAs to the MS, and transmits and receives signals to and from the MS in the selected FAs.

Abstract: A semiconductor device includes a device isolation region defining an active region in a substrate, and gate structures buried in the active region of the substrate. At least one of the gate structures includes a gate trench, a gate insulating layer conformally formed on an inner wall of the gate trench, a gate barrier pattern conformally formed on the gate insulating layer disposed on a lower portion of the gate trench, a gate electrode pattern formed on the gate barrier pattern and filling the lower portion of the gate trench, an electrode protection layer conformally formed on the gate insulating layer disposed on an upper portion of the gate trench to be in contact with the gate barrier pattern and the gate electrode pattern, a buffer oxide layer conformally formed on the electrode protection layer, and a gate capping insulating layer formed on the buffer oxide layer to fill the upper portion of the gate trench.

Abstract: A semiconductor device includes a device isolation region defining an active region in a substrate, and gate structures buried in the active region of the substrate. At least one of the gate structures includes a gate trench, a gate insulating layer conformally formed on an inner wall of the gate trench, a gate barrier pattern conformally formed on the gate insulating layer disposed on a lower portion of the gate trench, a gate electrode pattern formed on the gate barrier pattern and filling the lower portion of the gate trench, an electrode protection layer conformally formed on the gate insulating layer disposed on an upper portion of the gate trench to be in contact with the gate barrier pattern and the gate electrode pattern, a buffer oxide layer conformally formed on the electrode protection layer, and a gate capping insulating layer formed on the buffer oxide layer to fill the upper portion of the gate trench.

Abstract: An Internet Protocol (IP) address acquisition in a broadband wireless communication system is disclosed. A terminal includes a driver for loading one of a plurality Media Access Control (MAC) addresses for a multi-Frequency Allocation (FA) connection when the terminal is initialized; an interface for registering the loaded MAC address to use in an upper layer of a MAC layer; and a manager for acquiring an IP address using the registered MAC address when a network entry for at least one FA is complete.

Abstract: A semiconductor device includes a device isolation region defining an active region in a substrate, and gate structures buried in the active region of the substrate. At least one of the gate structures includes a gate trench, a gate insulating layer conformally formed on an inner wall of the gate trench, a gate barrier pattern conformally formed on the gate insulating layer disposed on a lower portion of the gate trench, a gate electrode pattern formed on the gate barrier pattern and filling the lower portion of the gate trench, an electrode protection layer conformally formed on the gate insulating layer disposed on an upper portion of the gate trench to be in contact with the gate barrier pattern and the gate electrode pattern, a buffer oxide layer conformally formed on the electrode protection layer, and a gate capping insulating layer formed on the buffer oxide layer to fill the upper portion of the gate trench.

Abstract: A semiconductor device includes a device isolation region defining an active region in a substrate, and gate structures buried in the active region of the substrate. At least one of the gate structures includes a gate trench, a gate insulating layer conformally formed on an inner wall of the gate trench, a gate barrier pattern conformally formed on the gate insulating layer disposed on a lower portion of the gate trench, a gate electrode pattern formed on the gate barrier pattern and filling the lower portion of the gate trench, an electrode protection layer conformally formed on the gate insulating layer disposed on an upper portion of the gate trench to be in contact with the gate barrier pattern and the gate electrode pattern, a buffer oxide layer conformally formed on the electrode protection layer, and a gate capping insulating layer formed on the buffer oxide layer to fill the upper portion of the gate trench.

Abstract: Semiconductor devices include an intrinsic semiconductor region on a substrate, a source region adjacent to a first side surface of the semiconductor region and doped with a p-type dopant, a drain region adjacent to a second side surface of the semiconductor region, a gate electrode on the semiconductor region, a source gate electrode on the source region, and a drain gate electrode on the drain region. The second side surface is a reverse side of the first side surface. The drain region is doped with a p-type dopant.

Abstract: A semiconductor memory device includes: a memory unit including a first memory sub region including a first memory cell and a second memory sub region including a second memory cell; a temperature information obtaining unit that obtains temperature information; a temperature estimation unit that estimates a first temperature of the first memory sub region and a second temperature of the second memory sub region based on the temperature information; a first sub region control unit that controls the first memory sub region based on the first temperature; and a second sub region control unit that controls the second memory sub region based on the second temperature.

Abstract: Semiconductor devices include an intrinsic semiconductor region on a substrate, a source region adjacent to a first side surface of the semiconductor region and doped with a p-type dopant, a drain region adjacent to a second side surface of the semiconductor region, a gate electrode on the semiconductor region, a source gate electrode on the source region, and a drain gate electrode on the drain region. The second side surface is a reverse side of the first side surface. The drain region is doped with a p-type dopant.

Abstract: A semiconductor device includes a device isolation region defining an active region in a substrate, and gate structures buried in the active region of the substrate. At least one of the gate structures includes a gate trench, a gate insulating layer conformally formed on an inner wall of the gate trench, a gate barrier pattern conformally formed on the gate insulating layer disposed on a lower portion of the gate trench, a gate electrode pattern formed on the gate barrier pattern and filling the lower portion of the gate trench, an electrode protection layer conformally formed on the gate insulating layer disposed on an upper portion of the gate trench to be in contact with the gate barrier pattern and the gate electrode pattern, a buffer oxide layer conformally formed on the electrode protection layer, and a gate capping insulating layer formed on the buffer oxide layer to fill the upper portion of the gate trench.

Abstract: A handover method and apparatus for reducing a time delay during handover in a communication system is provided. A Mobile Station (MS) transmits a serving Base Station (BS) a first message indicating that the MS will perform handover to a target BS and the first message includes information for requesting a second message indicating a response to the successful receipt of the first message.

Abstract: An apparatus and method for performing handover in a broadband wireless communication system are provided. A communication method includes broadcasting, by a Base Station (BS), a neighbor advertisement message including neighbor cell information through each Frequency Allocation (FA); analyzing the neighbor cell advertise message by a plurality of Media Access Control (MAC) processors of an Mobile Station (MS) to obtain FA configuration information of each neighbor cell; independently determining handover by the MAC processors of the MS; generating the start of handover by one MAC which first determines handover; and determining a handover target by the remaining MAC processors so that handover is performed to different FAs of the same BS of the MAC processor which generates the start of handover by using the FA configuration information of each neighbor cell.

Abstract: A semiconductor memory device includes: a memory unit including a first memory sub region including a first memory cell and a second memory sub region including a second memory cell; a temperature information obtaining unit that obtains temperature information; a temperature estimation unit that estimates a first temperature of the first memory sub region and a second temperature of the second memory sub region based on the temperature information; a first sub region control unit that controls the first memory sub region based on the first temperature; and a second sub region control unit that controls the second memory sub region based on the second temperature.

Abstract: A broadband wireless communication system is provided. A sending apparatus in the broadband wireless communication system includes a controller for distributing packets to a plurality of processors to transmit the packets in a multi-Frequency Allocation (FA) access mode; the plurality of the processors for processing the packet provided from the controller in a Media Access Control (MAC) layer; and a plurality of senders for encoding the packets provided from the corresponding processors in a physical layer and transmitting a signal generated through the physical layer encoding.

Abstract: An apparatus and method for supporting different frame structures in a broadband wireless communication system are provided. A communication method of a Base Station (BS) includes determining a frame structure to be provided. A MAP message including an indicator that indicates a new standard is generated, when the provided frame structure conforms to the new standard. The generated MAP message is transmitted by performing physical layer encoding thereon. Accordingly, signaling is defined to report a currently provided frame structure to an MS, and thus, a system can support different frame structures.

Abstract: In a communication system, a base station transmits a message including neighbor base station information to a mobile station, wherein neighbor base stations in the base station include m first type neighbor base stations and n second type neighbor base stations, the message includes an identifier dedicatedly allocated to the mobile station when the mobile station can get a service from one of the n second type neighbor base stations, the first type is different from the second type, the neighbor base station information includes information on the n second type neighbor base stations, and each of m and n is an integer identical to or greater than 1.