Patents by Inventor Min Ho Oh

Min Ho Oh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250178684
    Abstract: A walking robot pose estimation method is provided. The walking robot pose estimation method according to an embodiment of the present disclosure includes the calculation a kinematic factor considering data measured by an inertial measurement unit (IMU) mounted on the walking robot and joint kinematics while the walking robot is in motion, obtaining point cloud data with respect to the environment where the walking robot is located by using the LiDAR sensor mounted on it, obtaining image data with respect to the environment where the walking robot is located by using the image sensor mounted on it, data fusion operation of the kinematic factor, the point cloud data, and the image data, and pose estimation of the walking robot based on the fused data.
    Type: Application
    Filed: December 3, 2024
    Publication date: June 5, 2025
    Applicant: Korea Advanced Institute of Science and Technology
    Inventors: Hyun MYUNG, Kevin Christiansen MARSIM, Min Ho OH, Byeong Ho YU, Seung Jae LEE
  • Patent number: 10629624
    Abstract: A thin film transistor array panel includes a substrate, a gate insulating layer, an interface layer, and a semiconductor layer. The gate insulating layer is disposed on the substrate. The interface layer is disposed on the gate insulating layer. The semiconductor layer is disposed on the interface layer. The interface layer includes a fluorinated silicon oxide. The semiconductor layer includes a p-type oxide semiconductor material.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: April 21, 2020
    Assignees: SAMSUNG DISPLAY CO., LTD., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION
    Inventors: Jae Heung Ha, Jong Woo Kim, Ji Young Moon, Min Ho Oh, Seung Jae Lee, Yoon Hyeung Cho, Young Cheol Joo, Hyeong Joon Kim, Eun-Kil Park, Sang Jin Han
  • Publication number: 20180061865
    Abstract: A thin film transistor array panel includes a substrate, a gate insulating layer, an interface layer, and a semiconductor layer. The gate insulating layer is disposed on the substrate. The interface layer is disposed on the gate insulating layer. The semiconductor layer is disposed on the interface layer. The interface layer includes a fluorinated silicon oxide. The semiconductor layer includes a p-type oxide semiconductor material.
    Type: Application
    Filed: August 16, 2017
    Publication date: March 1, 2018
    Inventors: Jae Heung Ha, Jong Woo Kim, Ji Young Moon, Min Ho Oh, Seung Jae Lee, Yoon Hyeung Cho, Young Cheol Joo, Hyeong Joon Kim, Eun-Kil Park, Sang Jin Han
  • Patent number: 9741776
    Abstract: A method for manufacturing an organic light emitting diode display includes forming a thin-film transistor on a substrate, forming a protection layer by using a deposition method on an entire surface of the substrate, and forming an organic light emitting element on the protection layer. Forming the protection layer includes forming a first protection layer, a surface thereof including a first wrinkle, and forming a second protection layer on the first protection layer, a surface thereof including a second wrinkle. A first modulus value of the first protection layer is less than a second modulus value of the second protection layer by at least 300 MPa.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: August 22, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jae Heung Ha, Yong Tack Kim, Jong Woo Kim, Ji Young Moon, Min Ho Oh, Seung Jae Lee, Yoon Hyeung Cho
  • Publication number: 20170084677
    Abstract: A method for manufacturing an organic light emitting diode display includes forming a thin-film transistor on a substrate, forming a protection layer by using a deposition method on an entire surface of the substrate, and forming an organic light emitting element on the protection layer. Forming the protection layer includes forming a first protection layer, a surface thereof including a first wrinkle, and forming a second protection layer on the first protection layer, a surface thereof including a second wrinkle. A first modulus value of the first protection layer is less than a second modulus value of the second protection layer by at least 300 MPa.
    Type: Application
    Filed: April 12, 2016
    Publication date: March 23, 2017
    Inventors: Jae Heung HA, Yong Tack Kim, Jong Woo Kim, Ji Young Moon, Min Ho Oh, Seung Jae Lee, Yoon Hyeung Cho
  • Patent number: 6432151
    Abstract: Disclosed herein is a method of preparing silica slurry for wafer polishing. This method includes pre-treating relatively inexpensive and commercially available fumed or colloidal silica particles as a seed by a settling, a crushing using a ball mill and a paint shaker, and a sonication to produce an aqueous dispersion of the silica particles. The pre-treated silica particles are then combined with tetraethylorothosilicate as a precursor, an alcohol solvent and a base, and grown to a desired size by hydrolysis and polycondensation of the precursor, tetraethylorothosilicate. Then, the alcohol solvent, in which the silica particles are grown, are displaced with water by a vacuum distillation. The resulting aqueous dispersion of the grown silica dispersion is hydrothermally treated in an autoclave. Thus, this method allows the economical preparation of the spherical silica particles having a highly uniform size and a very high purity.
    Type: Grant
    Filed: August 22, 2000
    Date of Patent: August 13, 2002
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Jae Hyun So, Min Ho Oh, Sun Hyuck Bae, Seung Man Yang, Do Hyun Kim