Patents by Inventor Min-ho Yang
Min-ho Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11975296Abstract: A pore-filled ion exchange polyelectrolyte composite membrane from which the surface ion exchange polyelectrolyte has been removed and a method of manufacturing the same are provided. The ion exchange polyelectrolyte composite membrane exhibits low film resistance and low in-plane-direction swelling degree, and has a smaller film-thickness than a commercial film, and thus, can be used for various purposes. In addition, since the pore-filled ion exchange polyelectrolyte composite membrane is continuously manufactured through a roll-to-roll process, the manufacturing process is simple, and manufacturing costs can be greatly reduced.Type: GrantFiled: April 29, 2019Date of Patent: May 7, 2024Assignee: Toray Advanced Materials Korea Inc.Inventors: Young Woo Choi, Mi Soon Lee, Tae Young Kim, Young Gi Yoon, Beom Jun Kim, Min Ho Seo, Chi Young Jung, Jong Min Lee, Nam-jo Jeong, Seung Cheol Yang, Ji Yeon Choi
-
Publication number: 20240120566Abstract: The present disclosure relates to a method of recycling a positive electrode active material and a recycled positive electrode active material prepared by the same. More particularly, the present disclosure relates to a method of recycling a positive electrode active material, the method including step A of fragmenting a waste battery including a positive electrode, a separator, and a negative electrode to form waste battery scraps; step B of removing the negative electrode by jetting compressed air onto the waste battery scraps; and step C of treating the waste battery scraps from which the negative electrode has been removed with a solvent to remove the separator and obtain positive electrode scraps, and a recycled positive electrode active material prepared by the method.Type: ApplicationFiled: August 22, 2022Publication date: April 11, 2024Inventors: Min Seo KIM, Doo Kyung YANG, Se Ho PARK, Jeongbae LEE, Eunkyu SEONG, Yongsik SEO
-
Publication number: 20240121924Abstract: A water-cooled heat dissipation module assembly capable of cooling a power module of a vehicle driving inverter system using a battery or fuel cell. The water-cooled heat dissipation module assembly includes a housing unit provided in the form of a housing having an opening portion at least partially opened at one side thereof. The housing unit and at least a part of a rim region of the cooling unit are made of a plastic material, and the housing unit and the cooling unit are joined to each other by plastic welding using a laser.Type: ApplicationFiled: August 4, 2022Publication date: April 11, 2024Inventors: Kwan Ho RYU, Jeong Keun LEE, Min Woo LEE, Ju Hyun SUN, Tae Keun PARK, Kang Wook PARK, Lee Cheol JI, Hyeok Chul YANG, Tae Heon KIM, Keun Jae LEE
-
Publication number: 20240106020Abstract: Provided is a method for recovering and reusing an active material from a positive electrode scrap.Type: ApplicationFiled: August 1, 2022Publication date: March 28, 2024Inventors: Eun-Kyu SEONG, Min-Seo KIM, Se-Ho PARK, Yong-Sik SEO, Doo-Kyung YANG, Jeong-Bae LEE
-
Patent number: 11067564Abstract: A portable insulin resistance diagnosis device includes: a housing capable of being grasped by an outer periphery thereof and comprising a space formed therein; a sensor unit which protrudes towards the outside of the housing and detects glucose and proteins in blood when a blood sample of a target specimen is dropped on the sensor unit, a diagnosis unit, which is provided inside the housing, amplifying an electrical signal generated according to concentrations of the blood glucose and proteins detected in the sensor unit, converting the electrical signal into a digital signal, and determining whether insulin resistance is normal; and a display unit, which is provided on an external surface of the housing, displaying whether insulin resistance analyzed in the diagnosis unit is normal.Type: GrantFiled: April 29, 2016Date of Patent: July 20, 2021Assignees: INDUSTRY ACADEMIC COOPERATION FOUNDATION KEIMYUNG UNIVERSITY, KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGYInventors: Yun Seok Heo, Dae-Kyu Song, Su Jeong Shin, Min Ho Yang, Jae-hoon Han, Tae Jae Lee, Seok Jae Lee
-
Publication number: 20190356405Abstract: A full duplex-type base station for removing signal interference between half duplex-type an uplink terminal and a downlink terminal, includes: a channel estimation unit which estimates channel coefficients between the base station, uplink terminal and downlink terminal; a reception precoding matrix generation unit which generates a reception precoding matrix on the basis of a first code and a channel with the uplink terminal; and a transmission precoding matrix generation unit which generates a transmission precoding matrix on the basis of a second code that is orthogonal to the first code, and a channel with the downlink terminal, wherein the first code is used for generating a transmission signal of the uplink terminal, the second code is used for removing the transmission signal—including the first code—of the uplink terminal, which is received as an interference signal at the time the downlink terminal receives a signal from the base station.Type: ApplicationFiled: August 2, 2019Publication date: November 21, 2019Inventors: Dong Ku KIM, Kwang-Soon KIM, Min Ho YANG
-
Publication number: 20180292383Abstract: A portable insulin resistance diagnosis device includes: a housing capable of being grasped by an outer periphery thereof and comprising a space formed therein; a sensor unit which protrudes towards the outside of the housing and detects glucose and proteins in blood when a blood sample of a target specimen is dropped on the sensor unit, a diagnosis unit, which is provided inside the housing, amplifying an electrical signal generated according to concentrations of the blood glucose and proteins detected in the sensor unit, converting the electrical signal into a digital signal, and determining whether insulin resistance is normal; and a display unit, which is provided on an external surface of the housing, displaying whether insulin resistance analyzed in the diagnosis unit is normal.Type: ApplicationFiled: April 29, 2016Publication date: October 11, 2018Applicants: INDUSTRY ACADEMIC COOPERATION FOUNDATION KEIMYUNG UNIVERSITY, KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGYInventors: Yun Seok HEO, Dae-Kyu SONG, Su Jeong SHIN, Min Ho YANG, Jae-hoon HAN, Tae Jae LEE, Seok Jae LEE
-
Publication number: 20160352887Abstract: An electronic device is provided. The electronic device includes an operation of displaying at least one message on the display screen of a display, an operation of identifying context information related to the at least one message, and an operation of providing background information of a message display area of the display screen based on the identified context information. Accordingly, it is possible to enhance a user's interest in message communication.Type: ApplicationFiled: May 24, 2016Publication date: December 1, 2016Inventors: Min-Wook NA, Han-Kyung JEON, Min-Ho YANG, Eun-Bee JEON, Jeong-Hyun PANG, Min-Kyung HWANG, Geon-Soo KIM
-
Patent number: 8268525Abstract: A toner usable with electrophotography includes an iron (Fe) content in the toner is in a range of about 1.0×102 ppm to about 1.0×104 ppm and a circle equivalent diameter of a sectional area of an Fe agglomerating agent is in a range of about 1.0 nm to about 2.0×102 nm.Type: GrantFiled: January 20, 2010Date of Patent: September 18, 2012Assignee: SAMSUNG Electronics Co., Ltd.Inventors: Hae-ree Joo, Sung-jun Park, Jae-hwan Kim, Min-ho Yang, Kyeong Pang
-
Patent number: 8053366Abstract: Provided is an aluminum (Al) doped charge trap layer, a non-volatile memory device and methods of fabricating the same. The charge trap layer may include a plurality of silicon nano dots that trap charges and a silicon oxide layer that covers the silicon nano dots, wherein the charge trap layer is doped with aluminum (Al). The non-volatile memory device may include a substrate including a source and a drain on separate regions of the substrate, a tunneling film on the substrate contacting the source and the drain, the charge trap layer according to example embodiments, a blocking film on the charge trap layer, and a gate electrode on the blocking film.Type: GrantFiled: September 17, 2010Date of Patent: November 8, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Eun-ha Lee, Hlon-suck Baik, Kwang-soo Seol, Sang-jin Park, Jong-bong Park, Min-ho Yang
-
Publication number: 20110006358Abstract: Provided is an aluminum (Al) doped charge trap layer, a non-volatile memory device and methods of fabricating the same. The charge trap layer may include a plurality of silicon nano dots that trap charges and a silicon oxide layer that covers the silicon nano dots, wherein the charge trap layer is doped with aluminum (Al). The non-volatile memory device may include a substrate including a source and a drain on separate regions of the substrate, a tunneling film on the substrate contacting the source and the drain, the charge trap layer according to example embodiments, a blocking film on the charge trap layer, and a gate electrode on the blocking film.Type: ApplicationFiled: September 17, 2010Publication date: January 13, 2011Inventors: Eun-ha Lee, Hlon-suck Baik, Kwang-soo Seol, Sang-jin Park, Jong-bong Park, Min-ho Yang
-
Patent number: 7838422Abstract: Provided is an aluminum (Al) doped charge trap layer, a non-volatile memory device and methods of fabricating the same. The charge trap layer may include a plurality of silicon nano dots that trap charges and a silicon oxide layer that covers the silicon nano dots, wherein the charge trap layer is doped with aluminum (Al). The non-volatile memory device may include a substrate including a source and a drain on separate regions of the substrate, a tunneling film on the substrate contacting the source and the drain, the charge trap layer according to example embodiments, a blocking film on the charge trap layer, and a gate electrode on the blocking film.Type: GrantFiled: August 28, 2007Date of Patent: November 23, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Eun-ha Lee, Hion-suck Baik, Kwang-soo Seol, Sang-jin Park, Jong-bong Park, Min-ho Yang
-
Publication number: 20100196814Abstract: A toner usable with electrophotography includes an iron (Fe) content in the toner is in a range of about 1.0×102 ppm to about 1.0×104 ppm and a circle equivalent diameter of a sectional area of an Fe agglomerating agent is in a range of about 1.0 nm to about 2.0×102 nm.Type: ApplicationFiled: January 20, 2010Publication date: August 5, 2010Applicant: Samsung Electronics Co., LtdInventors: Hae-ree JOO, Sung-jun Park, Jae-hwan Kim, Min-ho Yang, Kyeong Pang
-
Patent number: 7632742Abstract: A Pendeo-epitaxy growth substrate and a method of manufacturing the same are provided. The Pendeo-epitaxy growth substrate includes a substrate, a plurality of pattern areas formed on the substrate in a first direction for Pendeo-epitaxy growth, and at least one solution blocking layer contacting the plurality of pattern areas and formed on the substrate in a second direction, thereby preventing contamination of a semiconductor device due to air gaps and reducing the percentage defects of the semiconductor device during a Pendeo-epitaxy growth process.Type: GrantFiled: January 9, 2007Date of Patent: December 15, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Ho-sun Paek, Tae-hoon Jang, Youn-joon Sung, Tan Sakong, Min-ho Yang
-
Publication number: 20080150010Abstract: Provided is an aluminum (Al) doped charge trap layer, a non-volatile memory device and methods of fabricating the same. The charge trap layer may include a plurality of silicon nano dots that trap charges and a silicon oxide layer that covers the silicon nano dots, wherein the charge trap layer is doped with aluminum (Al). The non-volatile memory device may include a substrate including a source and a drain on separate regions of the substrate, a tunneling film on the substrate contacting the source and the drain, the charge trap layer according to example embodiments, a blocking film on the charge trap layer, and a gate electrode on the blocking film.Type: ApplicationFiled: August 28, 2007Publication date: June 26, 2008Inventors: Eun-ha Lee, Hion-suck Baik, Kwang-soo Seol, Sang-jin Park, Jong-bong Park, Min-ho Yang
-
Publication number: 20070190755Abstract: A Pendeo-epitaxy growth substrate and a method of manufacturing the same are provided. The Pendeo-epitaxy growth substrate includes a substrate, a plurality of pattern areas formed on the substrate in a first direction for Pendeo-epitaxy growth, and at least one solution blocking layer contacting the plurality of pattern areas and formed on the substrate in a second direction, thereby preventing contamination of a semiconductor device due to air gaps and reducing the percentage defects of the semiconductor device during a Pendeo-epitaxy growth process.Type: ApplicationFiled: January 9, 2007Publication date: August 16, 2007Applicant: Samsung Electronics Co., Ltd.Inventors: Ho-sun Paek, Tae-hoon Jang, Youn-Joon Sung, Tan Sakong, Min-ho Yang
-
Publication number: 20070152283Abstract: A semiconductor device and a manufacturing method thereof for preventing gate electrode degradation and gate current leakage. The semiconductor device includes a gate insulating layer including an H-k (high dielectric) material on a semiconductor substrate, a barrier metal layer including a metal alloy on the gate insulating layer, and a gate electrode layer formed on the barrier metal layer. Illustratively, the barrier metal layer includes at least one of TaAlN (tantalum aluminum nitride) or TiAlN (titanium aluminum nitride). The barrier metal layer can include an oxidation-resistant material so that oxidation of the barrier metal layer is prevented during a subsequent annealing of the semiconductor device in an oxygen atmosphere. Thus, degradation of a gate electrode is prevented, and gate current leakage due to degradation of the gate electrode is prevented.Type: ApplicationFiled: October 23, 2006Publication date: July 5, 2007Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hion-suck BAIK, Eun-ha LEE, Hyung-suk JUNG, Sung-kee HAN, Min-ho YANG