Abstract: Electronic devices including intermetallic columns within vias are provided. Vias are filled with one or more pastes containing metal particles. Thermal treatment of the pastes within the vias converts the particles within the pastes to one or more intermetallic compounds that do not melt during next level packaging.

Abstract: A structure includes a first substrate having a first surface and a second substrate having a second surface facing the first surface; liquid crystal material disposed between the first and second surfaces; a first upstanding electrode disposed over the first surface and extending into the liquid crystal material towards the second surface; and a first planar electrode disposed upon the first surface and electrically connected with the first upstanding electrode. The first planar electrode at least partially surrounds the first upstanding electrode. A combination of the first upstanding electrode and the first planar electrode forms at least a portion of a pixel of a liquid crystal display. Various methods to fabricate the structure are also disclosed.

Abstract: A method for fabricating a thin film transistor includes printing source, drain and channel regions on a passivated transparent substrate, forming a gate dielectric over the channel region and forming a gate conductor over the gate dielectric. A permanent antireflective coating is deposited over the source region, drain region and gate electrode, and an interlevel dielectric layer is formed over the permanent antireflective coating. Openings in the permanent antireflective coating and the interlevel dielectric layer are formed to provide contact holes to the source region, drain region and gate electrode. A conductor is deposited in the contact holes to electrically connect to the source region, drain region and gate electrode. Thin film transistor devices and other methods are also disclosed.

Abstract: An interconnect structure that includes a substrate having an electrical component present therein, and a under-bump metallurgy (UBM) stack that is present in contact with a contact pad to the electrical component that is present in the substrate. The UBM stack includes a metallic adhesion layer that is direct contact with the contact pad to the electrical component, a copper (Cu) seed layer that is in direct contact with the metallic adhesion layer, a first nickel (Ni) barrier layer that is present in direct contact with copper (Cu) seed layer, and a layered structure of at least one copper (Cu) conductor layer and at least one second nickel (Ni) barrier layer present on the first nickel (Ni) barrier layer. A solder ball may be present on second nickel (Ni) barrier layer.

Abstract: A process comprises manufacturing an electromigration-resistant under-bump metallization (UBM) flip chip structure comprising a Cu layer by applying to the Cu layer a metallic reaction barrier layer comprising NiFe. The solder employed in the flip chip structure comprise substantially lead-free tin. A structure comprises a product produced by this process. In another embodiment a process comprises manufacturing an electromigration-resistant UBM Sn-rich Pb-free solder bump flip chip structure wherein the electromigration-resistant UBM structure comprises a four-layer structure, or a three-layer structure, wherein the four layer structure is formed by providing 1) an adhesion layer, 2) a Cu seed layer for plating, 3) a reaction barrier layer, and 4) a wettable layer for joining to the solder, and the three-layer structure is formed by providing 1) an adhesion layer, 2) a reaction barrier layer, and 3) a wettable layer.

Abstract: A structure includes a first substrate having a first surface and a second substrate having a second surface facing the first surface; liquid crystal material disposed between the first and second surfaces; a first upstanding electrode disposed over the first surface and extending into the liquid crystal material towards the second surface; and a first planar electrode disposed upon the first surface and electrically connected with the first upstanding electrode. The first planar electrode at least partially surrounds the first upstanding electrode. A combination of the first upstanding electrode and the first planar electrode forms at least a portion of a pixel of a liquid crystal display. Various methods to fabricate the structure are also disclosed.

Abstract: A structure includes a first substrate having a first surface and a second substrate having a second surface facing the first surface; liquid crystal material disposed between the first and second surfaces; a first upstanding electrode disposed over the first surface and extending into the liquid crystal material towards the second surface; and a first planar electrode disposed upon the first surface and electrically connected with the first upstanding electrode. The first planar electrode at least partially surrounds the first upstanding electrode. A combination of the first upstanding electrode and the first planar electrode forms at least a portion of a pixel of a liquid crystal display. Various methods to fabricate the structure are also disclosed.

Abstract: The present disclosure generally provides for an integrated circuit (IC) structure with a TSV, and methods of manufacturing the IC structure and the TSV. An IC structure according to embodiments of the present invention may include a through-semiconductor via (TSV) embedded within a substrate, the TSV having an axial end; and a metal cap contacting the axial end of the TSV, wherein the metal cap has a greater electrical resistivity than the TSV.

Abstract: The present disclosure generally provides for integrated circuit (IC) structures with through-semiconductor vias (TSV). In an embodiment, an IC structure may include a through-semiconductor via (TSV) embedded in a substrate, the TSV having a cap; a dielectric layer adjacent to the substrate; a metal layer adjacent to the dielectric layer; a plurality of vias each embedded within the dielectric layer and coupling the metal layer to the cap of the TSV at respective contact points, wherein the plurality of vias is configured to create a substantially uniform current density throughout the TSV.

Abstract: An HDMI cable, an HDMI connector and an HDMI interface for a high-definition video/audio apparatus are provided. The HDMI interface includes the HDMI connector and the HDMI cable. The HDMI connector includes a connecting terminal having an extending cable terminal arranged in parallel in a main body. The HDMI cable includes at least one connecting unit consisting of a plurality of parallel metal wires. An insulating unit covers an outside of a face of the connecting unit, in such a manner that the metal wires are parallel and isolated from each other. The present invention is using design of single row of the connector terminal and single row of the HDMI cable, to simplify an HDMI interface structure and reduce size and weight, and manual identification is not required for pin bit definitions, which simplifies production process, reduces the manual work, and greatly improves production efficiency.

Abstract: An adjustable focal length lens structure comprising a first adjustable focal length lens. The first adjustable focal length lens comprises an inner surface of a first side having a first curvature. The first adjustable focal length lens also comprises a first transparent conducting electrode on the first side. The first adjustable focal length lens also comprises an inner surface of a second side having a second curvature. The first adjustable focal length lens also comprises a second transparent conducting electrode on the second side. The first adjustable focal length lens also comprises one or more layers of a first liquid crystal material disposed between the inner surface of the first side and the inner surface of the second side, wherein the first liquid crystal material has two or more effective indices of refraction.

Abstract: An interconnect structure that includes a substrate having an electrical component present therein, and a under-bump metallurgy (UBM) stack that is present in contact with a contact pad to the electrical component that is present in the substrate. The UBM stack includes a metallic adhesion layer that is direct contact with the contact pad to the electrical component, a copper (Cu) seed layer that is in direct contact with the metallic adhesion layer layer, a first nickel (Ni) barrier layer that is present in direct contact with copper (Cu) seed layer, and a layered structure of at least one copper (Cu) conductor layer and at least one second nickel (Ni) barrier layer present on the first nickel (Ni) barrier layer. A solder ball may be present on second nickel (Ni) barrier layer.

Abstract: An interconnect structure that includes a substrate having an electrical component present therein, and a under-bump metallurgy (UBM) stack that is present in contact with a contact pad to the electrical component that is present in the substrate. The UBM stack includes a metallic adhesion layer that is direct contact with the contact pad to the electrical component, a copper (Cu) seed layer that is in direct contact with the metallic adhesion layer, a first nickel (Ni) barrier layer that is present in direct contact with copper (Cu) seed layer, and a layered structure of at least one copper (Cu) conductor layer and at least one second nickel (Ni) barrier layer present on the first nickel (Ni) barrier layer. A solder ball may be present on second nickel (Ni) barrier layer.

Abstract: A method for fabricating a multi-chip stacked structure includes joining multiple wafers with interconnect structures interposed between each set of adjacent wafers. As each wafer is added to the stack, the new wafer is thinned to expose a through silicon via and back side metallization is performed. After the last wafer has been so joined, the wafer stack is diced and then joined to a substrate with a final interconnect structure interposed between the final wafer and the substrate.

Abstract: A structure includes a first substrate having a first surface and a second substrate having a second surface facing the first surface; liquid crystal material disposed between the first and second surfaces; a first upstanding electrode disposed over the first surface and extending into the liquid crystal material towards the second surface; and a first planar electrode disposed upon the first surface and electrically connected with the first upstanding electrode. The first planar electrode at least partially surrounds the first upstanding electrode. A combination of the first upstanding electrode and the first planar electrode forms at least a portion of a pixel of a liquid crystal display. Various methods to fabricate the structure are also disclosed.

Abstract: A method for fabricating a thin film transistor includes printing source, drain and channel regions on a passivated transparent substrate, forming a gate dielectric over the channel region and forming a gate conductor over the gate dielectric. A permanent antireflective coating is deposited over the source region, drain region and gate electrode, and an interlevel dielectric layer is formed over the permanent antireflective coating. Openings in the permanent antireflective coating and the interlevel dielectric layer are formed to provide contact holes to the source region, drain region and gate electrode. A conductor is deposited in the contact holes to electrically connect to the source region, drain region and gate electrode. Thin film transistor devices and other methods are also disclosed.

Abstract: Embodiments of the invention include a lead-free solder interconnect structure and methods for making a lead-free interconnect structure. The structure includes a semiconductor substrate having a last metal layer, a copper pedestal attached to the last metal layer, a barrier layer attached to the copper pedestal, a barrier protection layer attached to the barrier layer, and a lead-free solder layer contacting at least one side of the copper pedestal.

Abstract: Embodiments of the invention include a lead-free solder interconnect structure and methods for making a lead-free interconnect structure. The structure includes a semiconductor substrate having a last metal layer, a copper pedestal attached to the last metal layer, a barrier layer attached to the copper pedestal, a barrier protection layer attached to the barrier layer, and a lead-free solder layer contacting at least one side of the copper pedestal.

Abstract: The beam bending of a MEMS device is minimized by reducing interfacial strength between a sacrificial layer and a MEMS structure.

Abstract: A method for fabricating a multi-chip stacked structure includes joining multiple wafers with interconnect structures interposed between each set of adjacent wafers. As each wafer is added to the stack, the new wafer is thinned to expose a through silicon via and back side metallization is performed. After the last wafer has been so joined, the wafer stack is diced and then joined to a substrate with a final interconnect structure interposed between the final wafer and the substrate.