Abstract: Systems, methods, and other embodiments associated with an integrated circuit that includes a plurality of parallel pillar structures is described. In one embodiment, an integrated circuit includes a series of layers. The series of layers include a plurality of pillar metals in each of the series of layers. Pillars within each of the series of layers are oriented to be parallel. Pillars in adjacent layers are aligned to be perpendicular. Each of the plurality of pillar metals is a rectangular segment of metal. The plurality of pillar metals form a reconvergent mesh grid. The series of layers includes a plurality of vias connecting the plurality of parallel pillar metals between the series of layers. Vias of the plurality of vias are located at intersections in the reconvergent mesh grid.

Abstract: Embodiments of an electromigration (EM) check scheme to reduce a pessimism on current density limits by checking wire context. This methodology, in an embodiment, includes applying existing electronic design automation (EDA) flows and tools to identify potentially-failing wires based on a worst-case EM check using conservative foundry current density limits. A more accurate, context-specific check can be performed on the potentially-failing wires to eliminate one or more of the potentially-failing wires if those wires do not experience worst-case conditions and meet current density limits based on an actual context of those wires. A designer can correct remaining wires which are not eliminated by the context-specific check.

Abstract: Systems, methods, and other embodiments associated with an integrated circuit that includes a plurality of parallel pillar structures is described. In one embodiment, an integrated circuit includes a series of layers. The series of layers include a plurality of pillar metals in each of the series of layers. Pillars within each of the series of layers are oriented to be parallel. Pillars in adjacent layers are aligned to be perpendicular. Each of the plurality of pillar metals is a rectangular segment of metal. The plurality of pillar metals form a reconvergent mesh grid. The series of layers includes a plurality of vias connecting the plurality of parallel pillar metals between the series of layers. Vias of the plurality of vias are located at intersections in the reconvergent mesh grid.

Abstract: Systems, methods, and other embodiments associated with an integrated circuit that includes a plurality of parallel pillar structures is described. In one embodiment, a system includes a design logic configured to analyze a design of an integrated circuit to identify open tracks on each layer by determining a location of structures in each layer of the design. The open tracks are spaces on each layer of the design that are free from structures that obstruct routing the plurality of pillar metals. The system also includes routing logic configured to successively route the plurality of pillar metals in each of the layers of the design based, at least in part, on the parameters and the location of the structures. The routing logic routes pillars of the plurality of pillar metals that are in adjacent layers to be perpendicular and pillar metals that are within a same layer of the design to be parallel.

Abstract: Implementations of the present disclosure involve methods and systems for performing an electromigration analysis of a microelectronic circuit design. In particular, the implementations describe provide for performing a hierarchical extraction of the design, determining an approximate positioning and connection of two or more components of the design and performing electromigration analysis on the design. In one implementation, an intelligent connectivity may be applied to the hierarchical extraction to achieve an approximate location of the connection points between the blocks of the design. In one example, the intelligent connectivity technique may utilize a coordinate grid related to the design to approximate the connection points between the blocks of the design.

Abstract: Implementations of the present disclosure involve methods and systems for performing an electromigration analysis of a microelectronic circuit design. In particular, the implementations describe provide for performing a hierarchical extraction of the design, determining an approximate positioning and connection of two or more components of the design and performing electromigration analysis on the design. In one implementation, an intelligent connectivity may be applied to the hierarchical extraction to achieve an approximate location of the connection points between the blocks of the design. In one example, the intelligent connectivity technique may utilize a coordinate grid related to the design to approximate the connection points between the blocks of the design.

Abstract: Systems, methods, and other embodiments associated with an integrated circuit that includes a plurality of parallel pillar structures is described. In one embodiment, a system includes a design logic configured to analyze a design of an integrated circuit to identify open tracks on each layer by determining a location of structures in each layer of the design. The open tracks are spaces on each layer of the design that are free from structures that obstruct routing the plurality of pillar metals. The system also includes routing logic configured to successively route the plurality of pillar metals in each of the layers of the design based, at least in part, on the parameters and the location of the structures. The routing logic routes pillars of the plurality of pillar metals that are in adjacent layers to be perpendicular and pillar metals that are within a same layer of the design to be parallel.