Abstract: An apparatus for processing digital display data is described, wherein the digital display data has a fixed number of pixels in each display line, and the apparatus has a horizontal averaging means and a vertical averaging means. The horizontal averaging means identifies pixel data corresponding to a first pixel, a second pixel, and a third pixel, where the first, second, and third pixels are consecutive pixels in the same line of display data, and then smoothes the intensity values of the first, second, and third pixels, after which the smoothed values are stored. The vertical averaging means for identifies pixel data corresponding to a fourth and fifth pixels, where the fourth and fifth pixels are vertically adjacent to each other, and then smoothes the intensity values of said fourth and fifth pixel data, and storing the resulting smoothed values.

Abstract: In a video controller system including a video memory and first and second pluralities of functional circuits which access the video memory, requests for access to the video memory among more than one of the functional circuits are arbitrated by two levels of arbitration. In the first level of arbitration, a buffer in each of said first pluralities of functional circuits temporarily stores data read from or to be written to the video memory. A priority is assigned to requests for access from each of the functional circuits. A low limit and a high limit are assigned for each of the buffers. Requests for access to the video memory from all of the functional circuits are monitored. Each of the buffers is monitored to indicate whether the amount of data in each buffer is below the low limit or above the high limit. Access to the video memory is granted first to any requesting ones of the functional circuits whose buffers are below the low limit in order of the assigned priority.

Abstract: An asynchronous video system provides for the appropriate pixel data to be displayed. The system maps display control signals into a memory clock while maintaining the appropriate relationship with pixel data. Therefore, the display control signals are generated using the memory clock. Hence, no synchronization circuit is necessary to ensure that the memory control circuit and display control circuit are running at the same frequency.