Abstract: The present disclosure includes apparatuses, methods, and systems for receiving executable instructions from volatile memory. In an example, a method can include storing executable instructions comprising a bootloader at a pre-defined memory address range in a non-volatile memory device of a solid state drive (SSD), copying the executable instructions from the pre-defined memory address range to a volatile memory device of the SSD in response to powering on the SSD, and transmitting the executable instructions from the volatile memory device to a host.

Abstract: Apparatuses, systems, and methods for using defrag levels to reduce data loss are provided herein. In a number of embodiments of the present disclosure, a method can include setting a first defrag level for a memory device, determining if a buffer is full while performing defrag operations on the memory device according to the first defrag level, setting a second defrag level for the memory device in response to determining the buffer is full while performing defrag operations according to the first defrag level.

Abstract: Methods, systems, and devices supporting an interface for refreshing non-volatile memory are described. In some examples, a host system may communicate with a memory system, where both the host system and the memory system may be included within a vehicle (e.g., an automotive system). The host system may receive an indication that the vehicle is powering down (e.g., shutting off an engine or lowering power output from a battery). The host system may switch from a first mode corresponding to a first power usage to a second mode corresponding to a second, lower power usage in response to the vehicle powering down, the second mode supporting initiation of a refresh operation at the memory device. The host system may transmit a refresh command to the memory system to refresh non-volatile memory while the vehicle is powered down if the host system is operating in the second mode of operation.

Abstract: Programming video data to different portions of memory is described herein. An example system includes a host interface, a memory device having a first portion and a second portion, and a controller coupled to the host interface and the memory device. The controller can be configured to program video data received via the host interface to the first portion of the memory device, and program video data received via the host interface to the second portion of the memory device instead of to the first portion of the memory device in response to receiving a signal that a trigger event has occurred.

Abstract: Exemplary methods, apparatuses, and systems include a communication port manager for controlling communication of sensor data. The communication port manager receives a set of sensor data from a plurality of data sensors of a vehicle management system of a vehicle. The communication port manager writes the set of sensor data to memory of the memory subsystem. The communication port manager receives, from a battery management system, a request to read the sensor data. The communication port manager sends the set of sensor data to the battery management system, wherein the battery management system uses a wireless connection to send the sensor data to a cloud system.

Abstract: Exemplary methods, apparatuses, and systems include a performance throttling manager for controlling performance levels of a memory subsystem using input voltages. The performance throttling manager monitors input voltages to a memory device to determine a current input voltage value, while the memory device is operating at a first performance level. The performance throttling manager detects that the current input voltage value satisfies a threshold voltage value. The performance throttling manager selects a second performance level that is lower than the first performance level and throttles the performance of the memory device in response to detecting that the current input voltage value satisfies a threshold voltage value.

Abstract: Exemplary methods, apparatuses, and systems include a retention latency manager for controlling memory access operations in computing systems based on latency of a set of data bits. The retention latency manager receives a set of data bits from a host. The retention latency manager writes a time stamp. The retention latency manager writes the set of data bits to a location in memory. The retention latency manager computes a time difference between a current time and the time stamp. The retention latency manager selects a set of trim settings using the time difference. The retention latency manager reads the set of data bits from the first location in memory using the set of trim settings.

Abstract: In some implementations, a memory device may configure a reflow critical data region in a non-volatile memory that is associated with at least one reflow protection measure for data stored in the reflow critical data region. The memory device may write a set of data to the reflow critical data region. The memory device may determine that a reflow process associated with the memory device has been completed. The memory device may reconfigure the reflow critical data region to remove the at least one reflow protection measure based on determining that the reflow process has been completed.

Abstract: Partitions within buffer memory, such as may be used as a cyclic buffer for caching or storage of time based telemetric sensor data, can be operated with different programming characteristics to provide a balance between total memory sub-system capacity and endurance. Received first time based telemetric sensor data can be written to one or more partitions or sub-partitions with different programming characteristics. One programming characteristic can provide a lesser data density and greater data endurance than another programming characteristic. The programming characteristic can be data density per memory cell. The different partitions or sub-partitions can be written to randomly, with equal probability, or another metric.

Abstract: Data flush at power loss can include a solid state drive (SSD) receiving a power loss notification from a host. In response to the power loss notification, the SSD can flush dirty pages from a logical-to-physical (L2P) mapping table cached in volatile memory of the SSD to an L2P mapping table stored in non-volatile memory of the SSD. In response to the power loss notification, the SSD can flush dirty pages from an L2P mapping table cached in volatile memory of the host to the L2P mapping table stored in non-volatile memory of the SSD. In response to the power loss notification, the SSD can flush time based telemetric sensor data from volatile memory to non-volatile memory of the SSD.

Abstract: A production host can learn the production state awareness (PSA) modes supported by a memory device and select a particular of one of the supported PSA modes. The memory device can receive host image data from the production host and write the host image data according to the selected PSA mode. The memory device can set a PSA state to load complete after writing the host image data. The memory device can thereby be better situated for being soldered to a memory sub-system.

Abstract: Apparatuses, systems, and methods for using defrag levels to reduce data loss are provided herein. In a number of embodiments of the present disclosure, a method can include setting a first defrag level for a memory device, determining if a buffer is full while performing defrag operations on the memory device according to the first defrag level, setting a second defrag level for the memory device in response to determining the buffer is full while performing defrag operations according to the first defrag level.

Abstract: A redundant multiport memory for vehicle applications can have different ports coupled to different hosts that are configured to provide advanced driver assistance system (ADAS) for the vehicle. Different multiport memory devices can provide primary or secondary storage of data for the hosts. At least one of the hosts can perform a functionality check on at least one of the multiport memory devices and make use of a second multiport memory device to which it is coupled if a first multiport memory device to which it is coupled fails the check.

Abstract: A memory sub-system can allocate a first portion of blocks of a memory device for storage of file system metadata based on a file system and a capacity of the memory device, write video data received from a host within a second portion of the blocks at a first data density, and write file system metadata within the first portion of the blocks at a second data density lesser than the first data density.

Abstract: Methods, systems, and devices for fast mode for a memory device are described. In some examples, a memory device may be initialized during a system boot procedure. The memory device may support multiple modes of operation, including at least a first mode that includes a first set of capabilities, and a second made that includes the first set of capabilities, as well as one or more additional capabilities. The memory device may perform the initialization while operating the memory device according to the first mode, which may include delaying one or more actions associated with the one or more additional capabilities. After the system boot procedure is complete, the memory device may operate according to the second mode, which may include performing an action delayed during the system boot.

Abstract: A redundant multiport memory for vehicle applications can have different ports coupled to different hosts that are configured to provide advanced driver assistance system (ADAS) for the vehicle. Different multiport memory devices can provide primary or secondary storage of data for the hosts. At least one of the hosts can perform a functionality check on at least one of the multiport memory devices and make use of a second multiport memory device to which it is coupled if a first multiport memory device to which it is coupled fails the check.

Abstract: A memory device and method of operation are described. The memory device may include memory cells of a first type that each store a single bit of information and memory cells of a second type that each store multiple bits of information. The memory cells of the first type may be more robust to extreme operating conditions than the second type but may have one or more drawbacks (e.g., lower density). The memory device may identify data to be written, and in response, may identify a temperature of the memory device. If the temperature is within a nominal operating range associated with a low risk of memory errors, the memory device may write the data to the memory cells of the second type. If the temperature is outside the nominal operating range, the memory device may write the data to the memory cells of the first type.

Abstract: A system to progressively generate responses configured to mitigate risk associated with row hammer attacks. Between two successive refreshing of memory cells in a memory device, increasing thresholds are used to detect row hammer attacks. For example, after a first alert of row hammer attacks is generated using a first lower threshold, a first operation associated with the first lower threshold is initiated to mitigate risk associated with row hammer attack; and a second higher threshold is used to detect row hammer attacks. After a second alert of row hammer attacks is generated using the second lower threshold, a second operation associated with the second lower threshold is initiated to mitigate risk associated with row hammer attack.

Abstract: A memory device and a host system configured to transmit, using serial peripheral interfaces, an item (e.g., a command, an address, or a data item) followed by a cyclic redundancy check value of the item using operations same as transmission of one or more bits of the item. If the received cyclic redundancy check value does not match with the cyclic redundancy check value computed from the received item, an interrupt signal can be transmitted via a control line of a serial peripheral interface bus to request re-transmission of the item. When the host system detects a transmission error in receiving data from the memory device the serial peripheral interface bus, the host system can terminate the read command and re-transmit the read command.

Abstract: A memory device and method of operation are described. The memory device may include NAND memory. The memory device may configure a host device to maintain a host-side buffer for data backup. When the memory device determines an error associated with attempting to write data to a page of memory in a memory block, the memory device may indicate the error to the host device. The host device may, based on receiving the indication of the error, transmit to the memory device a backup copy of the data and other impacted data from the circular buffer. The memory device may configure the host-side buffer to have at least a particular size based one or more structural or operational aspects of the memory device.