Patents by Inventor Minjun BAE

Minjun BAE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210104489
    Abstract: Provided are a wafer level package and a method of manufacturing the same, wherein an underfill sufficiently fills a space between a redistribution substrate and a semiconductor chip, thereby reducing warpage. The wafer level package includes a redistribution substrate including at least one redistribution layer (RDL), a semiconductor chip on the redistribution substrate, and an underfill filling a space between the redistribution substrate and the semiconductor chip. The underfill covers side surfaces of the semiconductor chip. The redistribution substrate includes a trench having a line shape and extending in a first direction along a first side surface of the semiconductor chip.
    Type: Application
    Filed: May 8, 2020
    Publication date: April 8, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jinwoo PARK, Jungho PARK, Dahye KIM, Minjun BAE
  • Patent number: 10950539
    Abstract: A redistribution subtrate, a method of fabricating the same, and a semiconductor package are provided. The method including forming a first conductive pattern; forming a first photosensitive layer on the first conductive pattern, the first photosensitive layer having a first through hole exposing a first portion of the first conductive pattern; forming a first via in the first through hole; removing the first photosensitive layer; forming a first dielectric layer that encapsulates the first conductive pattern and the first via, the first dielectric layer exposing a top surface of the first via; and forming a second conductive pattern on the top surface of the first via.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: March 16, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jongyoun Kim, Seokhyun Lee, Minjun Bae
  • Publication number: 20210020505
    Abstract: A method of manufacturing a semiconductor package is provided including forming a lower redistribution layer. A conductive post is formed on the lower redistribution layer. A semiconductor chip is mounted on the lower redistribution layer. A molding member is formed on the lower redistribution layer. An upper surface of the molding member is at a level lower than an upper surface of the conductive post. An insulating layer is formed on the molding member. An upper surface of the insulating layer is at a level higher than the upper surface of the conductive post. The insulating layer is etched to expose the upper surface of the conductive post. An upper redistribution layer is formed on the insulating layer. The upper redistribution layer is electrically connected to the conductive post.
    Type: Application
    Filed: February 21, 2020
    Publication date: January 21, 2021
    Inventors: Jaegwon Jang, Seokhyun Lee, Jongyoun Kim, Minjun Bae
  • Publication number: 20200091066
    Abstract: A redistribution subtrate, a method of fabricating the same, and a semiconductor package are provided. The method including forming a first conductive pattern; forming a first photosensitive layer on the first conductive pattern, the first photosensitive layer having a first through hole exposing a first portion of the first conductive pattern; forming a first via in the first through hole; removing the first photosensitive layer; forming a first dielectric layer that encapsulates the first conductive pattern and the first via, the first dielectric layer exposing a top surface of the first via; and forming a second conductive pattern on the top surface of the first via.
    Type: Application
    Filed: March 13, 2019
    Publication date: March 19, 2020
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jongyoun KIM, Seokhyun LEE, Minjun BAE