Abstract: Group III-N devices and methods including an etch control layer are disclosed, where the etch control layer is configured to facilitate a hybrid etch process for forming a gate contact aperture in a semiconductor device. In examples, a III-N gate stack is formed over a gate region of a substrate of the semiconductor device. An etch control layer is formed over the III-N gate stack. The hybrid etch process may include a dry etch stage that stops in the etch control layer, followed by a wet etch stage that stops on or in a III-N cap layer or a p-doped III-N layer of the III-N gate stack. A gate electrode is formed in the gate contact aperture, where the gate electrode may extend through the etch control layer, any intervening dielectric cap layers, and may contact the III-N cap layer or the p-doped III-N layer.

Abstract: Group III-N devices and methods including an etch control layer are disclosed, where the etch control layer is configured to facilitate a hybrid etch process for forming a gate contact aperture in a semiconductor device. In examples, a III-N gate stack is formed over a gate region of a substrate of the semiconductor device. An etch control layer is formed over the III-N gate stack. The hybrid etch process may include a dry etch stage that stops in the etch control layer, followed by a wet etch stage that stops on or in a III-N cap layer or a p-doped III-N layer of the III-N gate stack. A gate electrode is formed in the gate contact aperture, where the gate electrode may extend through the etch control layer, any intervening dielectric cap layers, and may contact the III-N cap layer or the p-doped III-N layer.