Abstract: The present invention relates to a composition for preventing or treating transplantation rejection or a transplantation rejection disease, comprising a novel compound and a calcineurin inhibitor. A co-administration of the present invention 1) reduces the activity of pathogenic Th1 cells or Th17 cells, 2) increases the activity of Treg cells, 3) has an inhibitory effect against side effects, such as tissue damage, occurring in the sole administration thereof, 4) inhibits various pathogenic pathways, 5) inhibits the cell death of inflammatory cells, and 6) increases the activity of mitochondria, in an in vivo or in vitro allogenic model, a transplantation rejection disease model, a skin transplantation model, and a liver-transplanted patient, and thus inhibits transplantation rejection along with mitigating side effects possibly occurring in the administration of a conventional immunosuppressant alone.

Abstract: An electrolyte for a lithium secondary battery is disclosed herein. In some embodiments, an electrolyte includes a lithium salt present in a concentration of 1.6 M to 5 M, an oligomer mixture including a first oligomer containing a unit represented by Formula 1 and a second oligomer containing a unit represented by Formula 2, and an organic solvent.

Abstract: One embodiment comprises: a cover member including an upper plate and a side plate connected to the upper plate; a housing arranged in the cover member; a bobbin arranged in the housing; a coil coupled to the bobbin; a magnet which is arranged in the housing and faces the coil; a base arranged under the bobbin; and a first buffer unit arranged on the top surface of the bobbin corresponding to or facing the upper plate of the cover member, wherein the cover member includes a protrusion part extending in the direction toward the bobbin from the upper plate, and the distance in the optical axis direction between the protrusion part and the top surface of the bobbin is no greater than the distance in the optical axis direction between the first buffer unit and the inner surface of the upper plate of the cover member.

Abstract: Disclosed are a solar cell apparatus, and a method of fabricating the same. The solar cell apparatus includes: dummy parts disposed on a support substrate; a plurality of solar cells disposed on the support substrate and disposed between the dummy parts; and a bus bar electrically connected to the solar cells and disposed between the support substrate and the dummy parts. Each of the solar cells and the dummy parts has a back electrode layer, a light absorbing layer, and a front electrode layer sequentially disposed on the support substrate.

Abstract: Disclosed is a solar cell module. The solar cell module includes a solar cell panel, and a protective part surrounding the solar cell panel.

Abstract: Disclosed are a solar cell apparatus, and a method of fabricating the same. The solar cell apparatus includes: dummy parts disposed on a support substrate; a plurality of solar cells disposed on the support substrate and disposed between the dummy parts; and a bus bar electrically connected to the solar cells and disposed between the support substrate and the dummy parts. Each of the solar cells and the dummy parts has a back electrode layer, a light absorbing layer, and a front electrode layer sequentially disposed on the support substrate.

Abstract: A method of fabricating a transistor in a semiconductor device includes forming a gate structure over a substrate, forming a first trench by etching the substrate on either side of the gate structure to a first depth, ion-implanting dopants of a first conductivity type to form a source/drain region in the substrate on the side of the gate structure with the first trench, etching the substrate on the side of the gate structure with the first trench to a second depth larger than the first depth to form a second trench, and growing an epitaxial layer within the second trench.

Abstract: A method of fabricating a transistor in a semiconductor device includes forming a gate structure over a substrate, forming a first trench by etching the substrate on either side of the gate structure to a first depth, ion-implanting dopants of a first conductivity type to form a source/drain region in the substrate on the side of the gate structure with the first trench, etching the substrate on the side of the gate structure with the first trench to a second depth larger than the first depth to form a second trench, and growing an epitaxial layer within the second trench.

Abstract: The present invention relates to a semiconductor device which is capable of simultaneously improving a short channel effect of a PMOS and the current of an NMOS and a method for manufacturing the same. The semiconductor device includes first and second gates formed over first and second areas of a semiconductor substrate, respectively; and first and second junction areas formed in a portion of the semiconductor substrate corresponding to both sides of the first gate and a portion of the semiconductor substrate corresponding to both sides of the second gate, and including a projection, respectively, wherein the projection of the first junction area has a height higher than the height of the projection of the second junction area, and the second junction area is formed such that it has a depth from the surface of the semiconductor substrate deeper than the depth of the first junction area.

Abstract: A method of fabricating a transistor in a semiconductor device includes forming a gate structure over a substrate, forming a first trench by etching the substrate on either side of the gate structure to a first depth, ion-implanting dopants of a first conductivity type to form a source/drain region in the substrate on the side of the gate structure with the first trench, etching the substrate on the side of the gate structure with the first trench to a second depth larger than the first depth to form a second trench, and growing an epitaxial layer within the second trench.

Abstract: Manufacturing a semiconductor device includes defining bulb-type trenches having spherical portions in a silicon substrate. Oxide layers are formed in surfaces of spherical portions of the bulb-type trenches by conducting an oxidation process for the silicon substrate having the bulb-type trenches defined therein. An insulation layer is formed on the entire surface of the silicon substrate including the surfaces of the bulb-type trenches, which have the oxide layers formed in the surfaces of the spherical portions thereof. Isolation trenches are defined by etching the insulation layer, whereby SOI structures having the oxide layers interposed between portions of the silicon substrate are formed.

Abstract: A semiconductor device having a porous insulation layer with a permeation prevention layer coating the pores for use in protecting against hydrogen permeation into source and drain areas is presented. The semiconductor device includes a conductive pattern, an insulation layer, and a permeation prevention layer. The conductive pattern is formed on a semiconductor substrate. The insulation layer is formed on a surface of the conductive pattern and includes a porous layer having a plurality of pores. The permeation prevention layer is formed on exposed surfaces of the pores in the porous layer.

Abstract: The present invention relates to a semiconductor device which is capable of simultaneously improving a short channel effect of a PMOS and the current of an NMOS and a method for manufacturing the same. The semiconductor device includes first and second gates formed over first and second areas of a semiconductor substrate, respectively; and first and second junction areas formed in a portion of the semiconductor substrate corresponding to both sides of the first gate and a portion of the semiconductor substrate corresponding to both sides of the second gate, and including a projection, respectively, wherein the projection of the first junction area has a height higher than the height of the projection of the second junction area, and the second junction area is formed such that it has a depth from the surface of the semiconductor substrate deeper than the depth of the first junction area.

Abstract: A semiconductor device includes a main gate formed on a semiconductor substrate and a source region and a drain region formed in a surface of the semiconductor substrate on opposite sides of the main gate. An internal gate formed within a portion of the main gate that adjoins the source region.

Abstract: A method of fabricating a transistor in a semiconductor device includes forming a gate structure over a substrate, forming a first trench by etching the substrate on either side of the gate structure to a first depth, ion-implanting dopants of a first conductivity type to form a source/drain region in the substrate on the side of the gate structure with the first trench, etching the substrate on the side of the gate structure with the first trench to a second depth larger than the first depth to form a second trench, and growing an epitaxial layer within the second trench.

Abstract: Manufacturing a semiconductor device includes defining bulb-type trenches having spherical portions in a silicon substrate. Oxide layers are formed in surfaces of spherical portions of the bulb-type trenches by conducting an oxidation process for the silicon substrate having the bulb-type trenches defined therein. An insulation layer is formed on the entire surface of the silicon substrate including the surfaces of the bulb-type trenches, which have the oxide layers formed in the surfaces of the spherical portions thereof. Isolation trenches are defined by etching the insulation layer, whereby SOI structures having the oxide layers interposed between portions of the silicon substrate are formed.

Abstract: A semiconductor device includes a gate formed over a semiconductor substrate; a junction region formed in a portion of the semiconductor substrate corresponding to both sides of the gate and including a projection, of which at least some portion thereof projects from the surface of the portion of the semiconductor substrate; and a contact plug formed so as to cover the projection.

Abstract: The present invention relates to a semiconductor device which is capable of simultaneously improving a short channel effect of a PMOS and the current of an NMOS and a method for manufacturing the same. The semiconductor device includes first and second gates formed over first and second areas of a semiconductor substrate, respectively; and first and second junction areas formed in a portion of the semiconductor substrate corresponding to both sides of the first gate and a portion of the semiconductor substrate corresponding to both sides of the second gate, and including a projection, respectively, wherein the projection of the first junction area has a height higher than the height of the projection of the second junction area, and the second junction area is formed such that it has a depth from the surface of the semiconductor substrate deeper than the depth of the first junction area.