Abstract: A semiconductor device includes a first chip and a second chip stacked on the first chip. The first chip includes a first substrate, a first upper pad on an upper surface of the first substrate, a first upper insulating layer surrounding a lower portion of the first upper pad and a sacrificial layer surrounding an upper portion of the first upper pad. The second chip includes a second substrate, a second upper pad on an upper surface of the second substrate and a second upper insulating layer surrounding the second upper pad, wherein a thickness of the second upper pad is less than a thickness of the first upper pad.

Abstract: A semiconductor package includes a semiconductor chip. The semiconductor chip includes a semiconductor substrate having a first surface and a second surface opposed to each other, an integrated circuit layer on the first surface of the semiconductor substrate, a wiring layer on the integrated circuit layer, a first pad and a second pad horizontally spaced apart from each other on the wiring layer and electrically connected to the wiring layer, a first bonding pad on the first pad and electrically connected to the first pad, a buried insulating pattern on the second pad, and a second bonding pad on the buried insulating pattern. The second bonding pad is electrically isolated from the second pad by the buried insulating pattern.

Abstract: A display apparatus can include a substrate having a first sub-pixel, a second sub-pixel, and a third sub-pixel, a reflective electrode layer including a first reflective electrode of the first sub-pixel, a second reflective electrode of the second sub-pixel, and a third reflective electrode of the third sub-pixel, and an anode electrode layer including a first anode electrode of the first sub-pixel, a second anode electrode of the second sub-pixel, and a third anode electrode of the third sub-pixel. A total thickness of the first reflective electrode and the first anode electrode is equal to a total thickness of the second reflective electrode and the second anode electrode, and is equal to a total thickness of the third reflective electrode and the third anode electrode.

Abstract: A semiconductor device includes a base structure comprising a first bonding pad and a first test pad, and a semiconductor chip comprising a second bonding pad being in contact with the first bonding pad of the base structure and a second test pad being in contact with the first test pad of the base structure. A width of the second bonding pad of the semiconductor chip is less than a width of the second test pad of the semiconductor chip. An air gap is provided between the first test pad of the base structure and the second test pad of the semiconductor chip.

Abstract: The present disclosure provides a system for detecting a defect in a photovoltaic wafer, the system including imaging equipment configured to obtain a target image of a photovoltaic wafer, and a defect detection device configured to determine presence or absence of at least one defect in the photovoltaic wafer in the target image, wherein the defect detection device is further configured to detect the presence or absence of the at least one defect, which includes a defective state with at least one fault in the photovoltaic wafer based on a fault detection deep learning model, and at least one black spot present on the photovoltaic wafer based on a black spot detection algorithm, and a normal state of the photovoltaic wafer.

Abstract: According to an embodiment disclosed herein, an electronic device may comprise a housing structure including a first housing and a second housing, a hinge structure that rotatably connects the first housing and the second housing and is configured to provide at least one folding axis serving as the center of rotation of the first housing or the second housing, and a flexible printed circuit board that extends from the inside of the first housing across the hinge structure and into the second housing. In an embodiment, a region, in the flexible printed circuit board, passing through the hinge structure may include a substrate layer, a shielding layer, and a signal line layer formed between the substrate layer and the shielding layer. In an embodiment, the signal line layer may include a signal line and a ground line that extend along a direction substantially perpendicular to the at least one folding axis and are arranged adjacent to each other.

Abstract: A semiconductor package comprises: a first substrate; a first pad on a top surface of the first substrate; a first conductive pattern on a bottom surface of the first pad; and a semiconductor chip on the top surface of the first substrate, wherein the semiconductor chip comprises: a semiconductor substrate; an interconnection layer on a bottom surface of the semiconductor substrate, the interconnection layer comprising an interconnection pattern; and a bonding pad on a bottom surface of the interconnection pattern, wherein the bonding pad is directly bonded to the first pad, wherein a width of the interconnection pattern is larger than a width of the bonding pad, wherein a width of the first conductive pattern is smaller than a width of the first pad, and wherein the interconnection pattern and the bonding pad comprise different materials.

Abstract: There is provided a semiconductor package with minimized physical damage and improved reliability in a structure in which a plurality of memory chips are stacked. The semiconductor package includes a base chip, a plurality of memory chips disposed on the base chip, and a sealing material sealing the plurality of memory chips on the base chip, wherein each of the plurality of memory chips is disposed on a center portion of an upper surface of the base chip, the plurality of memory chips include at least one first memory chip at a bottom thereof and at least one second memory chip disposed on the at least one first memory chip, each of the at least one first memory chip has a larger plan view area than each of the at least one second memory chip.

Abstract: An electronic device is provided. The electronic device includes communication circuitry, a display, a processor, and memory including instructions which, when executed by the processor, cause the electronic device to perform operations given below, wherein the instructions are configured to generate a virtual screen for mirroring a screen displayed on at least a partial region of the display, on the basis of configuration information related to a screen of an external electronic device connected through the communication circuitry, transmit the generated virtual screen to the external electronic device through the communication circuitry, receive changed configuration information from the external electronic device through the communication circuitry while the virtual screen is transmitted, change the virtual screen on the basis of the changed configuration information, and transmit the changed virtual screen to the external electronic device through the communication circuitry.

Abstract: A display device may include a display panel including a plurality of subpixels, a mode control circuit configured to control a driving mode by determining a state of a user, a compensation control circuit configured to control compensation for at least one of a driving voltage and a data signal according to the user's state, a data driving circuit configured to supply a compensated data signal to the display panel according to control of the compensation control circuit, and a power management circuit configured to supply a compensated driving voltage to the display panel according to control of the compensation control circuit.

Abstract: A display device includes a first substrate including a plurality of sub-pixels; each first electrode disposed on each of the plurality of sub-pixels; a light-emitting layer disposed on the first electrodes a second electrode disposed on the light-emitting layer, and a color conversion structure disposed over the plurality of sub-pixels, wherein the color conversion structure has different thicknesses in each of the sub-pixels.

Abstract: Disclosed is a display device including a first substrate having a plurality of sub-pixels areas corresponding to a plurality of sub-pixels. A first electrode is disposed on the substrate within each sub-pixel, and a light-emissive layer is disposed on each first electrode. A second electrode is disposed on the light-emissive layer. Reflective electrodes are also disposed on the substrate within the respective sub-pixels, and the reflective electrodes have different thicknesses among the sub-pixels. The variation in thickness allows the display device to control the emission characteristics of each sub-pixel, facilitating color differentiation without using a color filter.

Abstract: A wafer cleaning device includes a plurality of brush systems arranged in a line in a first direction and configured to clean a wafer. Each of the plurality of brush systems includes a body having a tube shape extending in the first direction, a nodule arranged on an outer surface of the body, and a driveshaft extending in the first direction and configured to integrally rotate with the body. The plurality of brush systems are configured to independently rotate with the first direction as a rotation axis.

Abstract: A soft haptic device and a local control method are disclosed. The soft haptic device includes a soft actuator. The soft actuator includes an electroactive polymer film, a patterned electrode, and a dielectric liquid injected between the electroactive polymer film and the patterned electrode. The soft actuator generates a reconfigurable shape such that a form of an output shape and a number of outputtable shapes are changed depending on the number of electrodes constituting the patterned electrode, a shape of the electrodes, and an arrangement of the electrodes.

Abstract: A semiconductor package may include a first semiconductor chip and a second semiconductor chip on a top surface thereof. The first semiconductor chip may include a first bonding pad on a top surface of a first semiconductor substrate and a first penetration via on a bottom surface of the first bonding pad and penetrating the first semiconductor substrate. The second semiconductor chip may include a second interconnection pattern on a bottom surface of a second semiconductor substrate and a second bonding pad on a bottom surface of the second interconnection pattern and coupled to the second interconnection pattern. The second bonding pad may be directly bonded to the first bonding pad. A width of the first penetration via may be smaller than that of the first bonding pad, and a width of the second interconnection pattern may be larger than that of the second bonding pad.

Abstract: A semiconductor package includes a first semiconductor chip including a first semiconductor layer, a first through-electrode that penetrates through the first semiconductor layer, a first bonding pad connected to the first through-electrode, and a first insulating bonding layer, and a second semiconductor chip on the first semiconductor chip and including a second semiconductor layer, a second bonding pad bonded to the first bonding pad, and a second insulating bonding layer bonded to the first insulating bonding layer, wherein the first insulating bonding layer includes a first insulating material, the second insulating bonding layer includes a first insulating layer that forms a bonding interface with the first insulating bonding layer and a second insulating layer on the first insulating layer, the first insulating layer includes a second insulating material, different from the first insulating material, and the second insulating layer includes a third insulating material, different from the second insulat

Abstract: A method of manufacturing a semiconductor package may include: preparing a semiconductor wafer including rear pads and a rear insulating layer surrounding the rear pads, the rear insulating layer including first recesses spaced apart from the rear pads in a first lateral direction; preparing second semiconductor chips including front pads and a front insulating layer surrounding the front pads, the front insulating layer including second recesses spaced apart from the front pads in the first lateral direction; forming an air gap between the first recesses and the second recesses in a vertical direction by disposing the second semiconductor chips on the semiconductor wafer, the rear pads contacting the front pads; and bonding the rear insulating layer and the front insulating layer to each other and bonding the rear pads and the front pads to each other by performing a thermal compression process.

Abstract: A heat pipe includes: a base plate; a capillary on the base plate and including a plurality of patterned portions connected to each other to form a closed loop; and a cover plate on one surface of the base plate and covering the capillary. Each of the plurality of patterned portions includes: a first capillary portion having a first diameter; a second capillary portion having a second diameter smaller than the first diameter; and a turn portion connecting the first capillary portion and the second capillary portion and being extended to be bent. The number of the turn portion per unit area is the greatest at a central portion of the base plate.

Abstract: Disclosed are semiconductor devices and their fabrication methods. The semiconductor device comprises lower and upper structures. The lower structure includes a first semiconductor substrate, a first pad, and a first dielectric layer. The upper structure includes a second semiconductor substrate, a second pad, and a second dielectric layer. The upper and lower structures are bonded to each other to allow the first and second pads to come into contact each other and to allow the first and second dielectric layers to come into contact each other. A first interface between the first and second pads is at a level different from that of a second interface between the first and second dielectric layers. A first area of the first pad is greater than a second area of the second pad. A second thickness of the second pad is different from a first thickness of the first pad.

Abstract: A display apparatus according to one embodiment of the present specification includes a substrate including a display area including a plurality of pixels, and a pad area near the display area, a pad disposed on the substrate in the pad area and provided as a plurality of pads, and a light shielding layer disposed between a plurality of adjacent pads.