Abstract: A semiconductor device including a substrate; a lower structure including a sealing layer on the substrate and a support layer on the sealing layer, the sealing layer and the support layer both including a semiconductor material; a mold structure on the lower structure and having an interlayer insulating film and a conductive film alternately stacked therein; a channel hole penetrating the mold structure; a channel structure extending along sidewalls of the channel hole; an isolation trench penetrating the mold structure and extending into the lower structure; and a poly liner extending along sidewalls of the isolation trench, the poly liner being connected to the lower structure and including the semiconductor material.

Abstract: A semiconductor device including a substrate; a lower structure including a sealing layer on the substrate and a support layer on the sealing layer, the sealing layer and the support layer both including a semiconductor material; a mold structure on the lower structure and having an interlayer insulating film and a conductive film alternately stacked therein; a channel hole penetrating the mold structure; a channel structure extending along sidewalls of the channel hole; an isolation trench penetrating the mold structure and extending into the lower structure; and a poly liner extending along sidewalls of the isolation trench, the poly liner being connected to the lower structure and including the semiconductor material.

Abstract: A semiconductor device including a substrate; a lower structure including a sealing layer on the substrate and a support layer on the sealing layer, the sealing layer and the support layer both including a semiconductor material; a mold structure on the lower structure and having an interlayer insulating film and a conductive film alternately stacked therein; a channel hole penetrating the mold structure; a channel structure extending along sidewalls of the channel hole; an isolation trench penetrating the mold structure and extending into the lower structure; and a poly liner extending along sidewalls of the isolation trench, the poly liner being connected to the lower structure and including the semiconductor material.

Abstract: A semiconductor device includes a plurality of channel structures on a substrate, each channel structure extending in a first direction perpendicular to the substrate, a common source extension structure including a first semiconductor layer having an n-type conductivity and a gate insulating layer between the substrate and the channel structures, a plurality of gate electrodes on the common source extension structure and spaced apart from each other on a sidewall of each of the channel structures in the first direction, and a common source region on the substrate in contact with the common source extension structure and including a second semiconductor layer having an n-type conductivity. An upper portion of the common source extension structure has a first width, and a lower portion of the common source extension structure has a second width smaller than the first width.

Abstract: A vertical semiconductor device includes a plurality of channel connection patterns, a lower insulation layer, a supporting layer, a stacked structure, and a channel structure. The channel connection patterns, on which the lower insulation layer is formed, contact a substrate. The supporting layer is formed on the lower insulation layer to be spaced apart from the channel connection patterns, and includes polysilicon doped with impurities. The stacked structure is formed on the supporting layer, and includes insulation layers and gate electrodes to form a memory cell string. The channel structure passes through the stacked structure, the supporting layer and the lower insulation layer, and includes a charge storage structure and a channel which contacts the channel connection patterns. The charge storage structure and the channel face the gate electrodes and the supporting layer. The supporting layer serves as a gate of a gate induced drain leakage (GIDL) transistor.

Abstract: A vertical semiconductor device includes a plurality of channel connection patterns, a lower insulation layer, a supporting layer, a stacked structure, and a channel structure. The channel connection patterns, on which the lower insulation layer is formed, contact a substrate. The supporting layer is formed on the lower insulation layer to be spaced apart from the channel connection patterns, and includes polysilicon doped with impurities. The stacked structure is formed on the supporting layer, and includes insulation layers and gate electrodes to form a memory cell string. The channel structure passes through the stacked structure, the supporting layer and the lower insulation layer, and includes a charge storage structure and a channel which contacts the channel connection patterns. The charge storage structure and the channel face the gate electrodes and the supporting layer. The supporting layer serves as a gate of a gate induced drain leakage (GIDL) transistor.

Abstract: A semiconductor device includes a plurality of channel structures on a substrate, each channel structure extending in a first direction perpendicular to the substrate, and having a gate insulating layer and a channel layer, a common source extension region including a first semiconductor layer having an n-type conductivity between the substrate and the channel structures, a plurality of gate electrodes on the common source extension region and spaced apart from each other on a sidewall of each of the channel structures in the first direction, and a common source region on the substrate in contact with the common source extension region and including a second semiconductor layer having an n-type conductivity, wherein the gate insulating layer of each of the channel structures extends to cover an upper surface and at least a portion of a bottom surface of the common source extension region.

Abstract: A semiconductor device includes a plurality of channel structures on a substrate, each channel structure extending in a first direction perpendicular to the substrate, and having a gate insulating layer and a channel layer, a common source extension region including a first semiconductor layer having an n-type conductivity between the substrate and the channel structures, a plurality of gate electrodes on the common source extension region and spaced apart from each other on a sidewall of each of the channel structures in the first direction, and a common source region on the substrate in contact with the common source extension region and including a second semiconductor layer having an n-type conductivity, wherein the gate insulating layer of each of the channel structures extends to cover an upper surface and at least a portion of a bottom surface of the common source extension region.

Abstract: A semiconductor device includes a plurality of channel structures on a substrate, each channel structure extending in a first direction perpendicular to the substrate, and having a gate insulating layer and a channel layer, a common source extension region including a first semiconductor layer having an n-type conductivity between the substrate and the channel structures, a plurality of gate electrodes on the common source extension region and spaced apart from each other on a sidewall of each of the channel structures in the first direction, and a common source region on the substrate in contact with the common source extension region and including a second semiconductor layer having an n-type conductivity, wherein the gate insulating layer of each of the channel structures extends to cover an upper surface and at least a portion of a bottom surface of the common source extension region.

Abstract: A vertical stack memory device includes a doped semiconductor substrate having a common source to which a source power is applied and a low band gap layer that is spaced apart from the common source, and the low band gap comprising low band gap materials. A stack gate structure has gate electrodes and insulation interlayer patterns that are alternately and vertically stacked on the substrate in a first direction. A channel structure penetrates through the stack gate structure in the first direction. The channel structure makes contact with the low hand gap layer. A charge storage structure is interposed between the stack gate structure and the channel structure. The charge storage structure is configured to selectively store charge and to provide the stored charge to a memory cell, the stack gate structure, and the channel structure.