Abstract: The present application provides a semiconductor structure and a manufacturing method thereof, relates to the technical field of semiconductors. The manufacturing method includes: providing a substrate, the substrate including a first semiconductor material layer, a silicon-germanium compound layer and a second semiconductor material layer that are stacked sequentially; forming, in the substrate, first trenches extending along a first direction and second trenches extending along a second direction, and the first trenches and the second trenches separating the substrate into a plurality of spaced pillar structures; doping the pillar structures, such that the silicon-germanium compound layer forms a channel region; and forming a dielectric layer on an outer peripheral surface of each of the pillar structures, and a gate on an outer peripheral surface of the dielectric layer, the gate being opposite to at least a part of the channel region.

Abstract: Embodiments relate to the field of semiconductor manufacturing technology, and more particularly, to a method for fabricating a semiconductor structure and a semiconductor structure. The method for fabricating a semiconductor structure provided by the embodiments of the present disclosure includes: providing a substrate including an array region and a peripheral region; forming a first mask layer covering the array region and the peripheral region on the substrate; forming a first device structure pattern on the first mask layer, and then forming a second device structure pattern on the first mask layer; and etching the substrate by using the first device structure pattern and the second device structure pattern as mask layer to form a peripheral region structure and an array region structure synchronously on the substrate. Technological processes are simplified, fabrication difficulties are reduced, and production efficiency is improved.

Abstract: A method for forming a semiconductor structure includes: providing a semiconductor substrate including a plurality of first semiconductor pillars and bit line isolation trenches arranged at intervals in a first direction; in which the bit line isolation trenches extend in a second direction, the first direction being perpendicular to the second direction; forming a bit line isolation layer in a bit line isolation trench; in which a gap is provided between the bit line isolation layer and the bit line isolation trench, in which the gap is located at a bottom corner of the bit line isolation trench and extends in the second direction, and exposes part of the bottom of the bit line isolation trench; etching a first semiconductor pillar in the first direction through the gap to form a bit line trench; forming a bit line in the bit line trench.

Abstract: The present invention discloses a method for preparing a lyophilized collagen powder and use thereof. The preparation method includes the following steps: filling a certain amount of a collagen solution in an ice cube mold, and freezing in an ultra-low-temperature environment; crushing the frozen solid collagen in a low-temperature crusher, and performing quick lyophilization, to obtain an intermediate lyophilized collagen powder; further weighing an amount of a collagen solution, and uniformly mixing with the intermediate lyophilized collagen powder prepared in the previous step; repeating the low-temperature crushing operation with the mixed collagen solution, to obtain a lyophilized collagen powder; and obtaining a final product after filling and sterilization by freezing irradiation at a low temperature. The collagen powder product is useful for hemostasis, or tissue filling after dissolution in sterile physiological saline.

Abstract: Embodiments relate to the field of semiconductor manufacturing technology, and more particularly, to a method for fabricating a semiconductor structure and a semiconductor structure. The fabricating method includes: providing a substrate including an array region and a peripheral region; and forming, on the substrate, a first mask layer covering the array region and the peripheral region, the first mask layer having a first device structure pattern directly facing the array region and a second device structure pattern directly facing the peripheral region. Through the method for fabricating a semiconductor structure, the first mask layer having the first device structure pattern and the second device structure pattern is formed on the substrate, and then the substrate is etched by using the first device structure pattern and the second device structure pattern as mask layer to synchronously form a peripheral region structure and an array region structure on the substrate.

Abstract: A semiconductor device includes a substrate. A method includes the following operations. Multiple first trenches extending in a first direction are formed in the substrate. Multiple second trenches extending in a second direction are formed in the substrate in which the first trenches are formed. The first direction is perpendicular to the second direction. A first depth of a first trench is equal to a second depth of a second trench. A first insulating layer, a conducting layer and a second insulating layer are formed in sequence in the first and second trenches. The conducting layer in the first trench is separated on a cross section in the second direction to form two bit lines connected to sidewalls at either side of the first trench and extending in the first direction. Word lines extending in the second direction are formed on the conducting layer in the first and second trenches.

Abstract: A semiconductor device includes a substrate. A method includes the following operations. Multiple first trenches extending in a first direction are formed in the substrate. Multiple second trenches extending in a second direction are formed in the substrate in which the first trenches are formed. The first direction is perpendicular to the second direction. A first depth of a first trench is equal to a second depth of a second trench. A first insulating layer, a conducting layer and a second insulating layer are formed in sequence in the first and second trenches. The conducting layer in the first trench is separated on a cross section in the second direction to form two bit lines connected to sidewalls at either side of the first trench and extending in the first direction. Word lines extending in the second direction are formed on the conducting layer in the first and second trenches.

Abstract: Embodiments relate to the field of semiconductor manufacturing technology, and more particularly, to a method for fabricating a semiconductor structure and a semiconductor structure. The method for fabricating a semiconductor structure provided by the embodiments of the present disclosure includes: providing a substrate including an array region and a peripheral region; forming a first mask layer covering the array region and the peripheral region on the substrate; forming a first device structure pattern on the first mask layer, and then forming a second device structure pattern on the first mask layer; and etching the substrate by using the first device structure pattern and the second device structure pattern as mask layer to form a peripheral region structure and an array region structure synchronously on the substrate. Technological processes are simplified, fabrication difficulties are reduced, and production efficiency is improved.

Abstract: Embodiments relate to the field of semiconductor manufacturing technology, and more particularly, to a method for fabricating a semiconductor structure and a semiconductor structure. The fabricating method includes: providing a substrate including an array region and a peripheral region; and forming, on the substrate, a first mask layer covering the array region and the peripheral region, the first mask layer having a first device structure pattern directly facing the array region and a second device structure pattern directly facing the peripheral region. Through the method for fabricating a semiconductor structure, the first mask layer having the first device structure pattern and the second device structure pattern is formed on the substrate, and then the substrate is etched by using the first device structure pattern and the second device structure pattern as mask layer to synchronously form a peripheral region structure and an array region structure on the substrate.

Abstract: Embodiments relate to the field of semiconductor manufacturing technology, and more particularly, to a semiconductor structure and a method for fabricating a semiconductor structure. The semiconductor structure includes a substrate including a first array region and a second array region. The first array region is provided with a first memory array comprising a plurality of first memory structures, and the second array region is provided with a second memory array comprising a plurality of second memory structures. Compared with related technologies where different memory structures are stacked on a substrate, in this embodiment, the plurality of first memory structures and the plurality of second memory structures are arranged side by side on the substrate, which is advantageous to simplifying fabrication processes and improving production efficiency.

Abstract: The present application provides a semiconductor structure and a manufacturing method thereof, relates to the technical field of semiconductors. The manufacturing method includes: providing a substrate, the substrate including a first semiconductor material layer, a silicon-germanium compound layer and a second semiconductor material layer that are stacked sequentially; forming, in the substrate, first trenches extending along a first direction and second trenches extending along a second direction, and the first trenches and the second trenches separating the substrate into a plurality of spaced pillar structures; doping the pillar structures, such that the silicon-germanium compound layer forms a channel region; and forming a dielectric layer on an outer peripheral surface of each of the pillar structures, and a gate on an outer peripheral surface of the dielectric layer, the gate being opposite to at least a part of the channel region.

Abstract: A method for forming a semiconductor structure includes: providing a semiconductor substrate including a plurality of first semiconductor pillars and bit line isolation trenches arranged at intervals in a first direction; in which the bit line isolation trenches extend in a second direction, the first direction being perpendicular to the second direction; forming a bit line isolation layer in a bit line isolation trench; in which a gap is provided between the bit line isolation layer and the bit line isolation trench, in which the gap is located at a bottom corner of the bit line isolation trench and extends in the second direction, and exposes part of the bottom of the bit line isolation trench; etching a first semiconductor pillar in the first direction through the gap to form a bit line trench; forming a bit line in the bit line trench.

Abstract: The present disclosure discloses a system for measuring a charge-to-mass ratio of an electrostatic atomization nozzle and a measurement method using the same. The system includes an electrostatic atomization nozzle, an upper cylinder, a lower cylinder, an ammeter, a liquid level tube, an ultrasonic level meter, a water storage tank, and a liquid pump. The electrostatic atomization nozzle, the upper cylinder, and the lower cylinder are sequentially connected from top to bottom. The ammeter is connected to the lower-cylinder flange. The liquid level tube is communicated with the lower cylinder. The ultrasonic level meter is mounted on an upper end of the liquid level tube. The water storage tank is located below a lower-cylinder water outlet pipe. The liquid pump can deliver a liquid in the water storage tank to the electrostatic atomization nozzle. Measurement data of the ammeter is acquired and processed by a computer in real time.

Abstract: The present disclosure discloses a system for measuring a charge-to-mass ratio of an electrostatic atomization nozzle and a measurement method using the same. The system includes an electrostatic atomization nozzle, an upper cylinder, a lower cylinder, an ammeter, a liquid level tube, an ultrasonic level meter, a water storage tank, and a liquid pump. The electrostatic atomization nozzle, the upper cylinder, and the lower cylinder are sequentially connected from top to bottom. The ammeter is connected to the lower-cylinder flange. The liquid level tube is communicated with the lower cylinder. The ultrasonic level meter is mounted on an upper end of the liquid level tube. The water storage tank is located below a lower-cylinder water outlet pipe. The liquid pump can deliver a liquid in the water storage tank to the electrostatic atomization nozzle. Measurement data of the ammeter is acquired and processed by a computer in real time.