Patents by Inventor Minoru Akaishi
Minoru Akaishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11193335Abstract: A polycrystalline diamond sintered material tool includes: a cemented carbide substrate, which is mainly composed of WC and includes Co; and a diamond layer containing a metal catalyst made of Co provided on the cemented carbide substrate. The average layer thickness of a Co rich layer formed in an interface between the cemented carbide substrate and the diamond layer is 30 ?m or less. CMAX/CDIA is 2 or less when CDIA is an average content of Co included in the diamond layer and CMAX is a peak value of a Co content in the Co rich layer. D/DO is less than 2 when D is an average grain size of WC particles in a region from the interface between the cemented carbide substrate and the diamond layer to 50 ?m toward an inside of the cemented carbide substrate; and DO is an average grain size of WC particles.Type: GrantFiled: November 21, 2016Date of Patent: December 7, 2021Assignee: MITSUBISHI MATERIALS CORPORATIONInventors: Toshihiko Matsuo, Wardoyo Akhmadi Eko, Minoru Akaishi
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Publication number: 20180371846Abstract: A polycrystalline diamond sintered material tool includes: a cemented carbide substrate, which is mainly composed of WC and includes Co; and a diamond layer containing a metal catalyst made of Co provided on the cemented carbide substrate. The average layer thickness of a Co rich layer formed in an interface between the cemented carbide substrate and the diamond layer is 30 ?m or less. CMAX/CDIA is 2 or less when CDIA is an average content of Co included in the diamond layer and CMAX is a peak value of a CO content in the Co rich layer. D/DO is less than 2 when D is an average grain size of WC particles in a region from the interface between the cemented carbide substrate and the diamond layer to 50 ?m toward an inside of the cemented carbide substrate; and DO is an average grain size of WC particles.Type: ApplicationFiled: November 21, 2016Publication date: December 27, 2018Applicant: MITSUBISHI MATERIALS CORPORATIONInventors: Toshihiko MATSUO, Wardoyo AKHMADI EKO, Minoru AKAISHI
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Patent number: 8657893Abstract: A method for producing a highly uniform and highly dense sintered cubic boron nitride compact having high hardness by sintering at a milder condition without a binder, is provided. The method includes deflocculating secondary particles in cubic boron nitride starting powders by dispersing the starting powders in a solution of a deflocculant; molding the green compact after removing the solution of the deflocculant from the starting powders; and then sintering the green compact in the presence of a supercritical fluid source in a supercritical state by pressing and heating the green compact together with the supercritical fluid source. The supercritical fluid source can be one or more selected from a group consisted of polyvinylidene chloride, polyvinyl chloride, polyethylene, polypropylene, polystyrene, a polyester and an ABS resin. In the sintering, the pressure is 5 GPa or higher, and the temperature is 1400° C. or higher.Type: GrantFiled: February 8, 2011Date of Patent: February 25, 2014Assignee: Mitsubishi Materials CorporationInventors: Akhmadi Eko Wardoyo, Itsurou Tajima, Minoru Akaishi
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Patent number: 8227341Abstract: An object is to prevent a failure, such as a wiring separation or a crack, in an insulating film under a copper wire, in a semiconductor device formed by wire-bonding the copper wire on a portion above the copper wiring. A semiconductor device according to the present invention includes a copper wiring formed above a semiconductor substrate, a plated layer formed so as to cover a top surface and side surfaces of the copper wiring, and a copper wire which is wire-bonded on the plated layer above the copper wiring.Type: GrantFiled: December 23, 2009Date of Patent: July 24, 2012Assignees: Semiconductor Components Industries, LLC, SANYO Semiconductor Co., Ltd.Inventors: Satoshi Onai, Minoru Akaishi, Hiroshi Ishizeki, Yoshiaki Sano
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Patent number: 8076781Abstract: A conventional semiconductor device has a problem that reduction of a connection resistance value between wiring layers is difficult because of an oxide film formed between the wiring layers. In a semiconductor device of this invention, a first metal layer is embeded in opening regions which connect a first wiring layer and a second wiring layer and an opening is formed in a spin coated resin film formed on the first metal layer. In the opening, a Cr layer forming a plating metal layer and a Cu plated layer are connected to each other. With this structure, the spaces among crystal grains in portions in the Cr layer on the first metal layer are wide, which causes the portions to be coarse. In the coarse portions in the Cr layer, an alloy layer formed of the second metal layer and the Cu plated layer is formed, and thus, the connection resistance value is reduced.Type: GrantFiled: April 16, 2008Date of Patent: December 13, 2011Assignees: SANYO Semiconductor Co., Ltd., Semiconductor Components Industries, LLCInventors: Yoshimasa Amatatsu, Minoru Akaishi, Satoshi Onai, Katsuya Okabe, Yoshiaki Sano, Akira Yamane
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Patent number: 8013442Abstract: In a semiconductor device according to the present invention, a plurality of opening regions 5 to 8 are formed in an insulating film on a pad electrode 3. A metal layer 9 formed on the pad electrode 3 has a plurality of concave portions 10 to 13 formed therein by covering the opening regions 5 to 8. Moreover, in a peripheral portion at a bottom of each of the concave portions 10 to 13 in the metal layer 9, the metal layer 9 and a Cu plating layer 19 react with each other. By use of this structure, the metal reaction area serves as a current path on the pad electrode 3. Thus, a resistance value on the pad electrode 3 is reduced.Type: GrantFiled: March 21, 2008Date of Patent: September 6, 2011Assignees: Semiconductor Components Industries, LLC, Sanyo Semiconductor Co., Ltd.Inventors: Yoshimasa Amatatsu, Minoru Akaishi, Satoshi Onai, Katsuya Okabe, Yoshiaki Sano, Akira Yamane
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Publication number: 20110192093Abstract: A method for producing a highly uniform and highly dense sintered cubic boron nitride compact having high hardness by sintering at a milder condition without a binder, is provided. The method includes deflocculating secondary particles in cubic boron nitride starting powders by dispersing the starting powders in a solution of a deflocculant; molding the green compact after removing the solution of the deflocculant from the starting powders; and then sintering the green compact in the presence of a supercritical fluid source in a supercritical state by pressing and heating the green compact together with the supercritical fluid source. The supercritical fluid source can be one or more selected from a group consisted of polyvinylidene chloride, polyvinyl chloride, polyethylene, polypropylene, polystyrene, a polyester and an ABS resin. In the sintering, the pressure is 5 GPa or higher, and the temperature is 1400° C. or higher.Type: ApplicationFiled: February 8, 2011Publication date: August 11, 2011Applicant: Mitsubishi Materials CorporationInventors: Akhmadi Eko Wardoyo, Itsurou Tajima, Minoru Akaishi
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Publication number: 20100164105Abstract: An object is to prevent a failure, such as a wiring separation or a crack, in an insulating film under a copper wire, in a semiconductor device formed by wire-bonding the copper wire on a portion above the copper wiring. A semiconductor device according to the present invention includes a copper wiring formed above a semiconductor substrate, a plated layer formed so as to cover a top surface and side surfaces of the copper wiring, and a copper wire which is wire-bonded on the plated layer above the copper wiring.Type: ApplicationFiled: December 23, 2009Publication date: July 1, 2010Applicants: SANYO Electric Co., Ltd., SANYO Semiconductior Co., Ltd.Inventors: Satoshi ONAI, Minoru Akaishi, Hiroshi Ishizeki, Yoshiaki Sano
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Patent number: 7719081Abstract: In a semiconductor device of the present invention, an epitaxial layer is formed on a P type single crystal silicon substrate. Isolation regions are formed in the epitaxial layer, and are divided into a plurality of element formation regions. An NPN transistor is formed in one of the element formation regions. An N type diffusion layer is formed between a P type isolation region and a P type diffusion layer which is used as a base region of the NPN transistor. This structure makes the base region and the isolation region tend not to be short-circuited. Hence, the breakdown voltage characteristics of the NPN transistor can be improved.Type: GrantFiled: December 8, 2006Date of Patent: May 18, 2010Assignee: Sanyo Electric Co., Ltd.Inventors: Mitsuru Soma, Hirotsugu Hata, Minoru Akaishi
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Patent number: 7560797Abstract: In a semiconductor device of the present invention, two epitaxial layers are formed on a P type single crystal silicon substrate. One of the epitaxial layers has an impurity concentration higher than that of the other epitaxial layer. The epitaxial layers are divided into a plurality of element formation regions by isolation regions. In one of the element formation regions, an NPN transistor is formed. Moreover, between a P type diffusion layer, which is used as a base region of the NPN transistor, and a P type isolation region, an N type diffusion layer is formed. Use of this structure makes it hard for a short-circuit to occur between the base region and the isolation region. Thus, the breakdown voltage characteristics of the NPN transistor can be improved.Type: GrantFiled: December 8, 2006Date of Patent: July 14, 2009Assignee: Sanyo Electric Co., Ltd.Inventors: Mitsuru Soma, Hirotsugu Hata, Minoru Akaishi
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Publication number: 20080258301Abstract: A conventional semiconductor device has a problem that reduction of a connection resistance value between wiring layers is difficult because of an oxide film formed between the wiring layers. In a semiconductor device of this invention, a first metal layer is embeded in opening regions which connect a first wiring layer and a second wiring layer and an opening is formed in a spin coated resin film formed on the first metal layer. In the opening, a Cr layer forming a plating metal layer and a Cu plated layer are connected to each other. With this structure, the spaces among crystal grains in portions in the Cr layer on the first metal layer are wide, which causes the portions to be coarse. In the coarse portions in the Cr layer, an alloy layer formed of the second metal layer and the Cu plated layer is formed, and thus, the connection resistance value is reduced.Type: ApplicationFiled: April 16, 2008Publication date: October 23, 2008Applicants: SANYO Electric Co., Ltd., SANYO Semiconductor Co., Ltd.Inventors: Yoshimasa Amatatsu, Minoru Akaishi, Satoshi Onai, Katsuya Okabe, Yoshiaki Sano, Akira Yamane
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Publication number: 20080237853Abstract: A conventional semiconductor device has a problem that reduction of a resistance value above a pad electrode is difficult because of an oxide film formed on a surface of the pad electrode. In a semiconductor device of this invention, an oxidation preventing metal layer is formed on a pad electrode, and the oxidation preventing metal layer is exposed at an opening region formed in a spin coat resin film at a portion above the pad electrode. In addition, a plating metal layer and a copper plated layer are formed on the oxidation preventing metal layer. With this structure, the resistance value above the pad electrode is reduced because the top surface of the pad electrode is difficult to oxidize, and the oxidation preventing metal layer having considerably smaller sheet resistivity than an oxidation film serves as part of a current path.Type: ApplicationFiled: March 27, 2008Publication date: October 2, 2008Applicants: SANYO Electric Co., Ltd., SANYO Semiconductor Co., Ltd.Inventors: Yoshimasa AMATATSU, Minoru AKAISHI, Satoshi ONAI, Katsuya OKABE, Yoshiaki SANO, Akira YAMANE
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Publication number: 20080230899Abstract: In a semiconductor device according to the present invention, a plurality of opening regions 5 to 8 are formed in an insulating film on a pad electrode 3. A metal layer 9 formed on the pad electrode 3 has a plurality of concave portions 10 to 13 formed therein by covering the opening regions 5 to 8. Moreover, in a peripheral portion at a bottom of each of the concave portions 10 to 13 in the metal layer 9, the metal layer 9 and a Cu plating layer 19 react with each other. By use of this structure, the metal reaction area serves as a current path on the pad electrode 3. Thus, a resistance value on the pad electrode 3 is reduced.Type: ApplicationFiled: March 21, 2008Publication date: September 25, 2008Applicants: SANYO Electric Co., Ltd., SANYO Semiconductor Co., Ltd.Inventors: Yoshimasa Amatatsu, Minoru Akaishi, Satoshi Onai, Katsuya Okabe, Yoshiaki Sano, Akira Yamane
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Publication number: 20070158754Abstract: In a semiconductor device of the present invention, two epitaxial layers are formed on a P type single crystal silicon substrate. In the epitaxial layers, P type buried diffusion layers and P type diffusion layers are formed, which form isolation regions. In this event, the P type buried diffusion layers are formed by being expanded from a surface of a first epitaxial layer. By use of this structure, lateral expansion widths of the P type buried diffusion layers are reduced. Thus, the device size of an NPN transistor can be reduced.Type: ApplicationFiled: December 7, 2006Publication date: July 12, 2007Applicant: SANYO ELECTRIC CO., LTD.Inventors: Mitsuru Soma, Hirotsugu Hata, Minoru Akaishi
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Publication number: 20070145520Abstract: In a semiconductor device of the present invention, two epitaxial layers are formed on a P type single crystal silicon substrate. One of the epitaxial layers has an impurity concentration higher than that of the other epitaxial layer. The epitaxial layers are divided into a plurality of element formation regions by isolation regions. In one of the element formation regions, an NPN transistor is formed. Moreover, between a P type diffusion layer, which is used as a base region of the NPN transistor, and a P type isolation region, an N type diffusion layer is formed. Use of this structure makes it hard for a short-circuit to occur between the base region and the isolation region. Thus, the breakdown voltage characteristics of the NPN transistor can be improved.Type: ApplicationFiled: December 8, 2006Publication date: June 28, 2007Applicant: SANYO ELECTRIC CO., LTD.Inventors: Mitsuru Soma, Hirotsugu Hata, Minoru Akaishi
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Publication number: 20070145530Abstract: In a semiconductor device of the present invention, an epitaxial layer is formed on a P type single crystal silicon substrate. Isolation regions are formed in the epitaxial layer, and are divided into a plurality of element formation regions. An NPN transistor is formed in one of the element formation regions. An N type diffusion layer is formed between a P type isolation region and a P type diffusion layer which is used as a base region of the NPN transistor. This structure makes the base region and the isolation region tend not to be short-circuited. Hence, the breakdown voltage characteristics of the NPN transistor can be improved.Type: ApplicationFiled: December 8, 2006Publication date: June 28, 2007Applicant: SANYO ELECTRIC CO., LTD.Inventors: Mitsuru Soma, Hirotsugu Hata, Minoru Akaishi
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Patent number: 7204921Abstract: A vacuum apparatus which can easily regenerate plasma is provided. A matching box used in the vacuum apparatus can vary the impedance thereof by varying the magnitudes of the inductance of variable inductance elements. Controlling the magnitude of direct current makes it possible to control the magnitudes of inductance of the variable inductance elements so that it is possible to carry out matching operation at high speed.Type: GrantFiled: September 9, 2003Date of Patent: April 17, 2007Assignee: ULVAC Inc.Inventors: Taro Yajima, Minoru Akaishi, Yoshikuni Horishita
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Publication number: 20070009374Abstract: Disclosed is a heat-resistant diamond composite sintered body, which is prepared by sintering an ultrafine-grain synthetic diamond powder having an average grain size of 200 nm or less, without using a sintering aid. The composite sintered body comprises a diamond crystal and a minute amount of non-diamond carbon as a product, and has a Vickers hardness of 85 GPa or more. The composite sintered body is produced by a method comprising enclosing in a Ta or Mo capsule a synthetic diamond powder having an average grain size of 200 nm or less, and heating and pressurizing using an ultrahigh-pressure synthesizing apparatus under thermodynamically stable conditions including a temperature of 2100° C. or more and a pressure of 7.7 GPa or more.Type: ApplicationFiled: November 19, 2003Publication date: January 11, 2007Applicants: JAPAN SCIENCE AND TECHNOLOGY AGENCY, NATIONAL INSTITUTE FOR MATERIALS SCIENCEInventors: Minoru Akaishi, Keigo Kawamura
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Publication number: 20060115408Abstract: Disclosed is a high-purity high-hardness ultrafine-grain diamond sintered body having a grain size of 100 nm or less, which is produced by subjecting an ultrafine-grain natural diamond powder having a grading range of zero to 0.1 ?m to a desilication treatment, freeze-drying the desilicated powder in solution, enclosing the freeze-dried powder in a Ta or Mo capsule without a sintering aid, and heating and pressurizing the capsule using an ultrahigh-pressure synthesizing apparatus at a temperature of 1700° C. or more and under a pressure of 8.5 GPa or more, which meet the conditions for diamond to be the thermodynamically stable. The present invention can synthesize a diamond sintered body under a lower pressure than that in a conventional method, with a diamond's original hardness and without containing any sintering aid.Type: ApplicationFiled: November 12, 2003Publication date: June 1, 2006Inventors: Minoru Akaishi, Keigo Kawamura
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Publication number: 20040139916Abstract: A vacuum apparatus which can easily regenerate plasma is provided. A matching box used in the vacuum apparatus can vary the impedance thereof by varying the magnitudes of the inductance of variable inductance elements. Controlling the magnitude of direct current makes it possible to control the magnitudes of inductance of the variable inductance elements so that it is possible to carry out matching operation at high speed.Type: ApplicationFiled: September 9, 2003Publication date: July 22, 2004Applicant: ULVAC INC.Inventors: Taro Yajima, Minoru Akaishi, Yoshikuni Horishita