Abstract: In a wafer level CSP package, with respect to signal wiring 9b disposed in a signal wiring disposition forbidden region 16 in the vicinity of external output terminals disposed in a package outer peripheral portion, since a stress generated at signal wiring 9 can be dispersed by disposing dummy wiring 9a around the signal wiring 9b or by expanding the width of the signal wiring itself, occurrences of cracks in a surface protective film can be readily suppressed.

Abstract: An upper surface of a semiconductor substrate includes a first portion where a dielectric film is provided, and a second portion where the dielectric film is not provided, wherein the second portion is located in the periphery of the first portion. The upper surface of the semiconductor substrate is covered with a sealing resin.

Abstract: A semiconductor device includes an external terminal, a plurality of first interconnections, an electrode, a conductor, and a second interconnection. The first interconnections are positioned below the external terminal. The electrode is positioned at the same level as the first interconnections and is electrically connected to the external terminal through the conductor. The second interconnection is positioned below the first interconnections and the electrode. The semiconductor device has a region where the shortest distance between an edge surface of the electrode and an edge surface of one of the first interconnections positioned most adjacent to the electrode is less than 0.11 times the total thickness of the conductor and the electrode. The second interconnection is positioned at a position different from that of the region in a thickness direction of the semiconductor device.

Abstract: In a wafer level CSP package, with respect to signal wiring 9b disposed in a signal wiring disposition forbidden region 16 in the vicinity of external output terminals disposed in a package outer peripheral portion, since a stress generated at signal wiring 9 can be dispersed by disposing dummy wiring 9a around the signal wiring 9b or by expanding the width of the signal wiring itself, occurrences of cracks in a surface protective film can be readily suppressed.

Abstract: A first mark formed simultaneously with the process step for forming a layer of metal interconnects is partly exposed at two parallel side surfaces of the separated semiconductor device or one side surface thereof to have a rectangular shape. This allows the identification of the orientation and product information of the semiconductor device in a small semiconductor device.