Abstract: In the control of DRAM having a plurality of banks by a pair of memory controllers, a high rate operation is enabled by a pipeline control even during an exchange of the privilege to use a memory. Specifically, a system memory 11 having a plurality of banks is shared by a memory controller 12 and an external device 13 for pipeline control. Both the memory controller 12 and the external device 13 include a monitor circuit which monitors an address and a control signal delivered by the counterpart. When the privilege to use a memory is to be transferred, a bank which is currently active is examined, and such access is immediately allowed when the access is to a bank which is not active. When the access is to a bank which is currently active, a standby interval is provided, and the access is allowed after its transition to an inactive condition. A pipeline control is enabled even during a changeover of the privilege to use the memory, thus allowing a high rate operation of a computer system.

Abstract: A DRAM access system is provided which can maintain high speed as in the burst DRAM, and can perform addressing by burst transfer unit as in the synchronous DRAM, and also have high compatibility with the conventional transfer system.

Abstract: A display terminal and apparatus for detecting the position of a light pen detecting field on a display surface at times the light pen is pointed to the light pen detecting field is described incorporating a column counter, scanning line counter, character row counter, light pen detecting field counter, and a light pen detecting line counter interconnected with an address generator, decoder, character code buffer, attribute buffer, font memory, light pen detection line generator mask line generator and scanning type display device. The invention overcomes the problem of misjudging the column address arising from variable delay times of the sensor signal from a light pen pointed to and sensing light from a display surface.