Abstract: An information processing apparatus comprises: a programmable circuit unit comprising a partial reconfiguration unit; a storage unit used by each of logic circuits configured in the partial reconfiguration unit; and a control unit that controls a logic circuit that becomes an access destination, in accordance with receiving an access command, wherein the control unit compares an address space indicating the access destination of the access command with the signal that is output from the partial reconfiguration unit due to the partial reconfiguration unit being configured using circuit information included in the configuration data, and controls to set as an access destination the logic circuit configured in the partial reconfiguration unit outputting the signal matching the address space indicating the access destination of the access command.

Abstract: A server apparatus includes a first receiving unit configured to receive print data transmitted from a client apparatus, a storage unit configured to store the print data of which reception has finished by the first receiving unit, and a second receiving unit configured to receive, from a printing apparatus, a request of print data, and a transmission unit configured to, in response to the request received by the second receiving unit, transmit a list of print data to the printing apparatus, the list of print data including identification information of the print data stored in the storage unit and identification information of print data of which reception has been started but has not finished by the first reception unit yet.

Abstract: An information processing apparatus, equipped with a WideIO memory device stacked on an SOC die including a CPU, and a method of controlling the same, are provide. The apparatus obtains temperature information of each of a plurality of memories of the WideIO memory device, and generates temperature distribution information of the WideIO memory device in accordance with respective execution of a plurality of function modules. Then, the apparatus determines a refresh rate of the WideIO memory device based on the maximum temperature of the WideIO memory device, decides a period, at which the refresh rate is determined, based on an operation mode of the information processing apparatus and a change rate of the maximum temperature for a predetermined time interval, and refreshes the WideIO memory device in accordance with the determined refresh rate.

Abstract: An information processing apparatus comprises: a programmable circuit unit comprising a partial reconfiguration unit; a storage unit used by each of logic circuits configured in the partial reconfiguration unit; and a control unit that controls a logic circuit that becomes an access destination, in accordance with receiving an access command, wherein the control unit compares an address space indicating the access destination of the access command with the signal that is output from the partial reconfiguration unit due to the partial reconfiguration unit being configured using circuit information included in the configuration data, and controls to set as an access destination the logic circuit configured in the partial reconfiguration unit outputting the signal matching the address space indicating the access destination of the access command.

Abstract: An information processing apparatus, equipped with a WideIO memory device stacked on an SOC die including a CPU, and a method of controlling the same, are provide. The apparatus obtains temperature information of each of a plurality of memories of the WideIO memory device, and generates temperature distribution information of the WideIO memory device in accordance with respective execution of a plurality of function modules. Then, the apparatus determines a refresh rate of the WideIO memory device based on the maximum temperature of the WideIO memory device, decides a period, at which the refresh rate is determined, based on an operation mode of the information processing apparatus and a change rate of the maximum temperature for a predetermined time interval, and refreshes the WideIO memory device in accordance with the determined refresh rate.

Abstract: A server apparatus includes a first receiving unit configured to receive print data transmitted from a client apparatus, a storage unit configured to store the print data of which reception has finished by the first receiving unit, and a second receiving unit configured to receive, from a printing apparatus, a request of print data, and a transmission unit configured to, in response to the request received by the second receiving unit, transmit a list of print data to the printing apparatus, the list of print data including identification information of the print data stored in the storage unit and identification information of print data of which reception has been started but has not finished by the first reception unit yet.

Abstract: An information processing apparatus according to one aspect of the present invention includes a wide IO memory device stacked on an SoC die that includes a CPU, acquires temperature information of multiple memories in the wide IO memory device, loads applications for executing separate functions to multiple memories, excluding the memory positioned above the circuit on the SoC die related to the function to be executed by the application, and, when the execution of the loaded application is instructed, executes the application loaded to the memory having a lower temperature that was acquired.

Abstract: An information processing apparatus according to one aspect of the present invention includes a wide IO memory device stacked on an SoC die that includes a CPU, acquires temperature information of multiple memories in the wide IO memory device, loads applications for executing separate functions to multiple memories, excluding the memory positioned above the circuit on the SoC die related to the function to be executed by the application, and, when the execution of the loaded application is instructed, executes the application loaded to the memory having a lower temperature that was acquired.

Abstract: An image processing apparatus comprises: a specification unit configured sequentially to determine, as a processing object, each of the blocks divided, and to compare data types of respective pixels in the block that is the processing object; a first determination unit configured to determine whether pixels included in a block including two data types to L (L=M×N) data types include a single type of attribute data; and an output unit configured to output, based on a determination by the first determination, a flag indicating that the block includes an attribute, a flag indicating a layout pattern of the block, a type of color data and a type of attribute data which are extracted from a pixel at a predefined position in the block.

Abstract: An image processing apparatus that enables to reduce needless consumption of memory band and control duplicated access to a main memory. A reading unit reads image data stored in a first storage unit and divides the image data into a plurality of rectangular areas of a predetermined size. A second storage unit stores image data in reference areas surrounding the rectangular areas, the reference areas having overlapped areas each of which includes a boundary between adjacent two rectangular areas. An image processing unit performs an image process based on the image data in the rectangular areas read by the reading unit and the image data in the reference areas stored in the second storage unit. A cache control unit controls to transfer the image data in the reference areas from the second storage unit to the image processing unit in response to a request from the image processing unit.

Abstract: An image forming apparatus that is capable of reducing power consumption by controlling electric power without employing a complex control in a unit of a small-scale module. The image forming apparatus executes processes concerning image formation in units of modules. A waiting unit makes a module wait an execution of a process until power supply stabilization time lapses after starting power supply to the module as a power control target. A measurement unit measures lapsed time until the power control target module has processed predetermined unit data after starting power supply. A determination unit determines whether the power supply to the power control target module is turned OFF based on the lapsed time acquired by the measurement unit.

Abstract: An image processing apparatus comprises: a specification unit configured sequentially to determine, as a processing object, each of the blocks divided, and to compare data types of respective pixels in the block that is the processing object; a first determination unit configured to determine whether pixels included in a block including two data types to L (L=M×N) data types include a single type of attribute data; and an output unit configured to output, based on a determination by the first determination, a flag indicating that the block includes an attribute, a flag indicating a layout pattern of the block, a type of color data and a type of attribute data which are extracted from a pixel at a predefined position in the block.

Abstract: An image processing apparatus that enables to reduce needless consumption of memory band and control duplicated access to a main memory. A reading unit reads image data stored in a first storage unit and divides the image data into a plurality of rectangular areas of a predetermined size. A second storage unit stores image data in reference areas surrounding the rectangular areas, the reference areas having overlapped areas each of which includes a boundary between adjacent two rectangular areas. An image processing unit performs an image process based on the image data in the rectangular areas read by the reading unit and the image data in the reference areas stored in the second storage unit. A cache control unit controls to transfer the image data in the reference areas from the second storage unit to the image processing unit in response to a request from the image processing unit.

Abstract: Correction for eliminating deformations of an image to be output from an image apparatus is executed while suppressing the processing load on the host computer side. A host computer acquires deformation information used to designate read addresses according to deformations of a scan line from a laser beam printer. A CPU (1) of the laser beam printer generates read addresses according to the deformation information to read out image data from a RAM, and transmits the readout image data to the laser beam printer. The laser beam printer (0) forms an image based on the image data received from the host computer (3000).

Abstract: Correction for eliminating deformations of an image to be output from an image apparatus is executed while suppressing the processing load on the host computer side. A host computer acquires deformation information used to designate read addresses according to deformations of a scan line from a laser beam printer. A CPU (1) of the laser beam printer generates read addresses according to the deformation information to read out image data from a RAM, and transmits the readout image data to the laser beam printer. The laser beam printer (0) forms an image based on the image data received from the host computer (3000).

Abstract: Correction for eliminating deformations of an image to be output from an image apparatus is executed while suppressing the processing load on the host computer side. A host computer acquires deformation information used to designate read addresses according to deformations of a scan line from a laser beam printer. A CPU (1) of the laser beam printer generates read addresses according to the deformation information to read out image data from a RAM, and transmits the readout image data to the laser beam printer. The laser beam printer (0) forms an image based on the image data received from the host computer (3000).

Abstract: Correction for eliminating deformations of an image to be output from an image apparatus is executed while suppressing the processing load on the host computer side. A host computer acquires deformation information used to designate read addresses according to deformations of a scan line from a laser beam printer. A CPU (1) of the laser beam printer generates read addresses according to the deformation information to read out image data from a RAM, and transmits the readout image data to the laser beam printer. The laser beam printer (0) forms an image based on the image data received from the host computer (3000).

Abstract: An arithmetic decoding method and apparatus process both binary image data and multi-level image data. When 4-bit image data is decoded, four complete sets of pairs of a more probable symbol and a state value or a probability estimate corresponding to pixels of four bitplanes are stored in corresponding ones of four predicted state memories. When less than 4-bit image data is to be decoded, a complete set of pairs of the more probable symbol and state value or the probability estimate corresponding to pixels of each bitplane are allocated to and stored in at least part of the four state memories. Ones of the pairs of the more probable symbol and the state value or the probability estimate are sequentially read from the four state memories and are used to sequentially decode the pixels.

Abstract: There are provided an inexpensive arithmetic decoding method and device that can process both of binary image data and multi-level image data, and a storage medium storing a program for executing the arithmetic decoding method. An arithmetic decoding device that decodes arithmetically encoded image data formed of at least one bitplane includes four predicted state memories that can be accessed separately, and an arithmetic operation section. When 4-bit image data is to be decoded, four complete sets of pairs of a more probable symbol and a state value or a probability estimate corresponding to pixels of four bitplanes of the 4-bit image data are stored in respective corresponding ones of the four predicted state memories.