Patents by Inventor Minoru Kanabara

Minoru Kanabara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory device comprising thin film memory transistors
    Patent number: 5278790
    Abstract: A latch circuit is provided between a column switch connected to the input/output sides for selecting data lines and a tristate buffer connected to the write side of a memory array, or between the column switch and a sense amplifier connected to the readout side of the memory array. The latch circuit has a capacity corresponding to a plurality of data contents in the tristate buffer or the sense amplifier. While data set in a portion of the latch circuit is being output, the next data can be set in another portion of the latch circuit.
    Type: Grant
    Filed: June 4, 1991
    Date of Patent: January 11, 1994
    Assignee: Casio Computer Co., Ltd.
    Inventor: Minoru Kanabara