Abstract: An image reading system comprising a display panel with an image display area formed by a plurality of display pixels which emits display light and displays an image in a viewing field side corresponding to a display signal from the image display area; a transparent substrate which has a read area provided in a viewing field side of the display panel; a plurality of photosensors formed in the read area above the transparent substrate; a driver circuit section formed in an outer side of the read area as one unit with the photosensors; a transparent conductive film for electrostatic protection is provided in an upper part of a plurality of photosensors and the driver circuit section; and comprises a photosensor panel which reads an image of a detectable object placed on the read area that penetrated at least some of the display light emitted from the image display area.

Abstract: The level shift circuit in the semiconductor circuit of the invention has a configuration comprising an input stage inverter circuit which inputs an input signal having a first voltage amplitude and outputs an inverted signal of this input signal, an output stage inverter circuit which inputs at least the output signal of the input stage inverter circuit and the output signal has a second voltage amplitude larger than the first voltage amplitude and a bootstrap circuit section which boosts a voltage value of input signal voltage of the output stage inverter circuit and the potential difference of the input signal and the output signal is held as a voltage component. The level shift circuit of each circuit is a Thin-Film Transistor at least using a semiconductor layer composed of amorphous silicon having single channel polarity as a switching element.

Abstract: An image reading system comprising a display panel with an image display area formed by a plurality of display pixels which emits display light and displays an image in a viewing field side corresponding to a display signal from the image display area; a transparent substrate which has a read area provided in a viewing field side of the display panel; a plurality of photosensors formed in the read area above the transparent substrate; a driver circuit section formed in an outer side of the read area as one unit with the photosensors; a transparent conductive film for electrostatic protection is provided in an upper part of a plurality of photosensors and the driver circuit section; and comprises a photosensor panel which reads an image of a detectable object placed on the read area that penetrated at least some of the display light emitted from the image display area.

Abstract: The level shift circuit in the semiconductor circuit of the invention has a configuration comprising an input stage inverter circuit which inputs an input signal having a first voltage amplitude and outputs an inverted signal of this input signal, an output stage inverter circuit which inputs at least the output signal of the input stage inverter circuit and the output signal has a second voltage amplitude larger than the first voltage amplitude and a bootstrap circuit section which boosts a voltage value of input signal voltage of the output stage inverter circuit and the potential difference of the input signal and the output signal is held as a voltage component. The level shift circuit of each circuit is a Thin-Film Transistor at least using a semiconductor layer composed of amorphous silicon having single channel polarity as a switching element.

Abstract: A shift register includes stages, outputting an output signal from each stage. The stage includes a first transistor which outputs an output signal inputted into one terminal from the previous stage via the other terminal, when an output signal is inputted into its control terminal. A second transistor has a control terminal connected to the other terminal of the first transistor, accumulates charges in a capacity of a wiring between the control terminal and the other terminal of the first transistor by a clock signal inputted into one terminal and outputs the clock signal from one terminal. A circuit displaces a potential of the wiring to a predetermined level when the output signal is inputted from the subsequent stage, and holds the potential of the wiring at a predetermined level until the output signal is inputted.

Abstract: In a shift register having stages each formed from three to six NMOS transistors, a transistor, which outputs an output signal when an ON voltage is applied to the gate, outputs an output signal from the source. Simultaneously, the gate voltage is increased by the parasitic capacitance between the gate and source. For this reason, the voltage of the output signal rises, and the output signal output from each stage does not attenuate.

Abstract: Each of stages RS(1), RS(2), . . . of a shift register is constituted by six TFTs. A ratio of a channel width and a channel length (W/L) of each of these TFTs 1 to 6 is set in accordance with a transistor characteristic of each TFT in such a manner that the shift register normally operates for a long time even at a high temperature.

Abstract: A shift register includes stages, outputting an output signal from each stage. The stage includes a first transistor which outputs an output signal inputted into one terminal from the previous stage via the other terminal, when an output signal is inputted into its control terminal. A second transistor has a control terminal connected to the other terminal of the first transistor, accumulates charges in a capacity of a wiring between the control terminal and the other terminal of the first transistor by a clock signal inputted into one terminal and outputs the clock signal from one terminal. A circuit displaces a potential of the wiring to a predetermined level when the output signal is inputted from the subsequent stage, and holds the potential of the wiring at a predetermined level until the output signal is inputted.

Abstract: Each of stages RS(1), RS(2), . . . of a shift register is constituted by six TFTS. A ratio of a channel width and a channel length (W/L) of each of these TFTS 1 to 6 is set in accordance with a transistor characteristic of each TFT in such a manner that the shift register normally operates for a long time even at a high temperature.

Abstract: A display apparatus comprises a liquid crystal display panel, gate driver circuit for scanning gate lines of the display panel, drain driver circuit for supplying the display data to drain lines of the display panel, level modulator circuit coupled to the display panel and control circuit. The control circuit determines that video data represents a still image data, stoped the operation of the drain driver circuit and activates the level modulator circuit. The level modulator circuit reads out from display signals from the display panel and re-writes display signals to the display panel in order to display the still image on the display panel. In this manner, the electric power consumed by the drain circuit can be conserved when the display apparatus displays the still image.

Abstract: A display driving apparatus includes a matrix display device for displaying an image. The matrix display device has switching elements and data written elements connected to the switching elements. The switching elements and the data written elements are arranged in rows and columns to form a matrix. A plurality of scan lines are arranged in a predetermined number of rows, with each row of the plurality of scan lines being connected to respective ones of the switching elements arranged along a corresponding row of the matrix. A plurality of data lines are connected to the switching elements for supplying lines of display data to be displayed on successive rows of the scan lines, and a data line driver circuit is connected to the switching elements via the data lines for supplying the switching elements connected to successive rows of the scan lines with the lines of display data.

Abstract: An active matrix array of display elements and nine drain line drivers are formed on a substrate. The drain line drivers are separated into three groups each containing three drain line drivers. Individual drain lines are connected to different drain line drivers in a layout order. Clock signals, which are obtained by frequency-dividing a D-clock signal to one ninth and which have phases shifted from one another by 120 degrees, are supplied via three clock signal lines that commonly connect associated drain line drivers in the individual groups in parallel. All the drain line drivers in each group are connected in parallel by a data signal line. Thinned video data signals obtained by separating input video data by three are supplied via the three data signal lines group by group.

Abstract: A liquid crystal device includes a TFT or active element substrate on which TFTs and pixel electrodes are arranged in the form of a matrix, a counter substrate having a counter electrode formed thereon and arranged to oppose the active element substrate, a polymer dispersed liquid crystal layer arranged between the active element substrate and the counter substrate and having a polymer resin and a liquid crystal which are dispersed, and a fluorescent film arranged on the pixel electrode. The device displays an image by controlling scattering, absorption, and transmission of light passing through the polymer dispersed liquid crystal layer. The phosphor film converts part of supplied light into fluorescent light having a predetermined wavelength and outputs colored light. Light used for a display is increased in intensity by the fluorescent light emitted from the phosphor film, thereby displaying a bright image.

Abstract: A liquid crystal display device in which TFTs and liquid crystal (LC) capacitances are connected in series between data lines and a common electrode, and photoelectric conversion elements are connected in parallel to the LC capacitances.

Abstract: A TFT array has a plurality of gate lines and a plurality of drain lines formed on a transparent insulating substrate. The gate lines intersect with the drain lines. TFTs are formed at the intersections of the gate lines and the drain lines. An opaque film is formed above the gate lines, the drain lines, and the TFTs, allowing no passage of light passing through the gaps between the transparent electrode, on the one hand, and the gate and drain lines, on the other hand. Therefore, when the TFT array is incorporated into a liquid-crystal display, the display will display high-contrast images.

Abstract: A TFT is formed on a transparent insulative substrate, and includes a gate electrode, a gate insulating film, a semiconductor film which has a channel portion, source and drain electrodes. An insulating film is formed on the TFT so as to cover at least the drain electrode and the gate insulating film. A transparent electrode is formed on at least part of insulating film except for a portion above the channel portion on the semiconductor film. The transparent electrode is electrically connected to the source electrode via a through hole which is formed on the insulating film at a position of the source electrode.

Abstract: First, a gate metal layer, a gate insulating film, a semiconductor layer, an n-type semiconductor layer, and an ohmic metal layer formed on a substrate in the order mentioned. Then, the film and the layers are patterned into those having the same shape and size. Next, a source metal layer and a drain metal layer are formed on the ohmic metal layer. Further, a portion of the ohmic metal layer, a portion of said source metal layer, and a portion of said drain metal layer are etched, thereby forming a channel portion. Finally, a transparent electrode is formed on the source metal layer, thus manufacturing a TFT. Since the film and the layer, the major components of the TFT, are sequentially formed, and are patterned simultaneously, the TFT can be manufacture with high yield. Further, since the transparent electrode is formed on the uppermost layer, i.e., the source metal layer, the pixel has a great opening ratio.

Abstract: A thin film transistor comprising a gate electrode, a gate insulating film, and a semiconductor layer, which have the same shape and the same size and stacked one upon another. The transistor further comprises an n-type semiconductor layer formed on the semiconductor layer, an ohmic electrode formed on the n-type semiconductor layer, and a source electrode and a drain electrode both formed on the ohmic electrode. Further, a transparent electrode is electrically connected to the source electrode. The thin film transistor has no step portions. Therefore, the transistor can be manufactured with high yield, and forms a pixel having a high opening ratio.

Abstract: A sense amplifier circuit includes an amplifier including first and second inverter circuits which each have a pair of thin film transistors and are connected in a cross-coupled configuration, a precharging thin film transistor connected between the first and second inverter circuits, input transfer gates respectively connected between the first and second inverter circuits and first and second input terminals, and output transfer gate respectively connected between the first and second inverter circuits and first and second input terminals. With the above construction, the precharging thin film transistor is made active to precharge the amplifier and then the transfer gates are operated to permit an input signal to be input to the amplifier, thereby causing the input signal to be discriminated between two values and amplified.

Abstract: Each of stages RS(1), RS(2), . . . of a shift register is constituted by six TFTs. A ratio of a channel width and a channel length (W/L) of each of these TFTs 1 to 6 is set in accordance with a transistor characteristic of each TFT in such a manner that the shift register normally operates for a long time even at a high temperature.