Patents by Inventor Minoru Kimura

Minoru Kimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11936514
    Abstract: A processing apparatus includes a virtualization control unit configured to virtualize hardware, and a network providing unit configured to provide a network function by using a resource virtualized by the virtualization control unit.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: March 19, 2024
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Kotaro Mihara, Toshifumi Sano, Nobuhiro Kimura, Minoru Sakuma
  • Publication number: 20210251310
    Abstract: A down jacket 1 has a face side fabric, a lining and feathers, and in addition, a strip of tape. The strip of tape extends between the face side fabric and the lining along a seam portion and is sewn together with the face side fabric and the lining. The strip of tape has a teaseled portion projecting from a surface of the strip of tape as a trap portion for trapping the feathers accommodated. The teaseled portion is formed on both a side of the strip of tape facing the face side fabric and a side of the strip of tape facing the lining.
    Type: Application
    Filed: February 10, 2021
    Publication date: August 19, 2021
    Applicant: SANKEI CO., LTD.
    Inventors: Minoru Kimura, Osamu Takahara
  • Patent number: 9744558
    Abstract: The present invention is intended to solve a problem that a coating film has an uneven thickness in the case where a coating target 1 has a stepped portion extending in a predetermined direction on its coating surface. To solve the problem, a follow-up coating is performed along the stepped portion S extending in the predetermined direction after coating of the entire coating surface of the coating target 1 so that paint mist adheres more to a relatively-recessed side of the stepped portion S.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: August 29, 2017
    Assignee: MAZDA MOTOR CORPORATION
    Inventors: Masafumi Shinoda, Minoru Kimura, Tatsuo Tsuneoka, Fumi Hirano
  • Publication number: 20150273496
    Abstract: The present invention is intended to solve a problem that a coating film has an uneven thickness in the case where a coating target 1 has a stepped portion extending in a predetermined direction on its coating surface. To solve the problem, a follow-up coating is performed along the stepped portion S extending in the predetermined direction after coating of the entire coating surface of the coating target 1 so that paint mist adheres more to a relatively-recessed side of the stepped portion S.
    Type: Application
    Filed: March 11, 2013
    Publication date: October 1, 2015
    Applicant: MAZDA MOTOR CORPORATION
    Inventors: Masafumi Shinoda, Minoru Kimura, Tatsuo Tsuneoka, Fumi Hirano
  • Patent number: 8791574
    Abstract: In a manufacturing method of a semiconductor device having a multilevel interconnect layer including a low-k layer, a two-step cutting technique is used for dicing. After formation of a groove in a semiconductor wafer with a tapered blade, the groove is divided with a straight blade thinner than the groove width. The multilevel interconnect layer portion is cut while being covered with a tapered face and then the wafer is separated with a thin blade which is not brought into contact with the multilevel interconnect layer portion. The wafer can thus be diced without damaging a relatively fragile low-k layer.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: July 29, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Toshihiko Akiba, Minoru Kimura, Masao Odagiri
  • Publication number: 20130062747
    Abstract: In a manufacturing method of a semiconductor device having a multilevel interconnect layer including a low-k layer, a two-step cutting technique is used for dicing. After formation of a groove in a semiconductor wafer with a tapered blade, the groove is divided with a straight blade thinner than the groove width. The multilevel interconnect layer portion is cut while being covered with a tapered face and then the wafer is separated with a thin blade which is not brought into contact with the multilevel interconnect layer portion. The wafer can thus be diced without damaging a relatively fragile low-k layer.
    Type: Application
    Filed: September 13, 2012
    Publication date: March 14, 2013
    Inventors: TOSHIHIKO AKIBA, Minoru Kimura, Masao Odagiri
  • Patent number: 8298963
    Abstract: With a recent shrinking semiconductor process, insulating layers formed between interconnect layers are becoming thin. To avoid parasitic capacitance between them, materials of a low dielectric constant have been used for an insulating layer in a multilevel interconnect. Low-k materials, however, have low strength compared with the conventional insulating layers. Porous low-k materials are structurally fragile. The invention therefore provides a manufacturing method of a semiconductor device having a multilevel interconnect layer including a low-k layer. According to the method, in a two-step cutting system dicing in which after formation of a groove in a semiconductor water with a tapered blade, the groove is divided with a straight blade thinner than the groove width, the multilevel interconnect layer portion is cut while being covered with a tapered face and then the wafer is separated with a thin blade which is not brought into contact with the multilevel interconnect layer portion.
    Type: Grant
    Filed: January 20, 2010
    Date of Patent: October 30, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Toshihiko Akiba, Minoru Kimura, Masao Odagiri
  • Publication number: 20100219068
    Abstract: A harmful gas treatment apparatus and a water treatment apparatus uses an electrochemical device provided with a solid electrolyte membrane having ion conductivity. A first electrochemical device provided with an anode on one surface of a hydrogen ion conductive electrolyte membrane and a cathode on the other surface thereof is combined with a second electrochemical device provided with an anode on one surface of a hydroxyl ion conductive electrolyte membrane and a cathode on the other surface thereof. Both cathodes are disposed so as to face each other within an electrochemical reaction tank. Each of the cathodes is provided with TiO2 as a metal oxide and Pt as a platinum group supported on a porous body having functions to occlude, concentrate and reduce harmful substances as a reducing catalyst. Thus, a water vapor partial pressure and an oxygen partial pressure on the both cathodes is reduced, making it possible to enhance hydrogen generation efficiency at the normal temperature and constant current.
    Type: Application
    Filed: February 23, 2007
    Publication date: September 2, 2010
    Applicants: Mitsubishi Electric Corporation, Kumamoto University
    Inventors: Shiro Yamauchi, Minoru Kimura, Shigeru Yamaji, Masato Machida
  • Publication number: 20100181681
    Abstract: With a recent shrinking semiconductor process, insulating layers formed between interconnect layers are becoming thin. To avoid parasitic capacitance between them, materials of a low dielectric constant have been used for an insulating layer in a multilevel interconnect. Low-k materials, however, have low strength compared with the conventional insulating layers. Porous low-k materials are structurally fragile. The invention therefore provides a manufacturing method of a semiconductor device having a multilevel interconnect layer including a low-k layer. According to the method, in a two-step cutting system dicing in which after formation of a groove in a semiconductor water with a tapered blade, the groove is divided with a straight blade thinner than the groove width, the multilevel interconnect layer portion is cut while being covered with a tapered face and then the wafer is separated with a thin blade which is not brought into contact with the multilevel interconnect layer portion.
    Type: Application
    Filed: January 20, 2010
    Publication date: July 22, 2010
    Inventors: Toshihiko AKIBA, Minoru KIMURA, Masao ODAGIRI
  • Patent number: 7759224
    Abstract: A technique capable of stably releasing chips from a dicing tape, includes grinding a back surface of a semiconductor wafer, while adhering a pressure sensitive adhesive tape to a circuit forming surface of the semiconductor wafer formed with an integrated circuit, to achieve a predetermined thickness and forcibly oxidizing the back surface of the semiconductor wafer. Then, the pressure sensitive adhesive tape adhered to the circuit forming surface of the semiconductor wafer is released, and a dicing tape is adhered to the back surface of the semiconductor wafer. Further, the semiconductor wafer is divided by dicing it into individual chips, and then the back surface of the chip is pressed by way of the dicing tape, thereby releasing the chips from the dicing tape.
    Type: Grant
    Filed: July 9, 2008
    Date of Patent: July 20, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Chuichi Miyazaki, Yoshiyuki Abe, Toshihide Uematsu, Minoru Kimura, Kazunari Suzuki, Masao Odagiri, Hideyuki Suga, Manabu Takata
  • Publication number: 20080286948
    Abstract: A technique capable of stably releasing chips from a dicing tape, includes grinding a back surface of a semiconductor wafer, while adhering a pressure sensitive adhesive tape to a circuit forming surface of the semiconductor wafer formed with an integrated circuit, to achieve a predetermined thickness and forcibly oxidizing the back surface of the semiconductor wafer. Then, the pressure sensitive adhesive tape adhered to the circuit forming surface of the semiconductor wafer is released, and a dicing tape is adhered to the back surface of the semiconductor wafer. Further, the semiconductor wafer is divided by dicing it into individual chips, and then the back surface of the chip is pressed by way of the dicing tape, thereby releasing the chips from the dicing tape.
    Type: Application
    Filed: July 9, 2008
    Publication date: November 20, 2008
    Inventors: Chuichi Miyazaki, Yoshiyuki Abe, Toshihide Uematsu, Minoru Kimura, Kazunari Suzuki, Masao Odagiri, Hideyuki Suga, Manabu Takata
  • Patent number: 7452599
    Abstract: This invention provides flame-generated fine silica particles having an average particle size of 0.05 to 1 ?m, wherein a fractal structure parameter ?1 at length scales ranging from 50 nm to 150 nm and a fractal structure parameter ?2 at length scales ranging from 150 nm to 353 nm satisfy the following formulas (1) and (2): ?0.0068S+2.548??1??0.0068S+3.748??(1) ?0.0011S+1.158??2??0.0011S+2.058??(2) wherein S is a BET specific surface area (m2/g) of the fine silica particles, in the measurement of small-angle X-ray scattering. When used as a filler for a semiconductor-encapsulation resin or when used as a filler for a polishing agent or for a coating layer for ink jet papers, the fine silica particles are available at high content without substantial enhancement of the viscosity. Besides, when used as a filler for the resin, the fine silica particles improve the strength of the molding compound.
    Type: Grant
    Filed: December 25, 2003
    Date of Patent: November 18, 2008
    Assignee: Tokuyama Corporation
    Inventors: Masakazu Ohara, Minoru Kimura, Hiroo Aoki
  • Patent number: 7452787
    Abstract: A technique capable of stably releasing chips from a dicing tape, includes grinding a back surface of a semiconductor wafer, while adhering a pressure sensitive adhesive tape to a circuit forming surface of the semiconductor wafer formed with an integrated circuit, to achieve a predetermined thickness and forcibly oxidizing the back surface of the semiconductor wafer. Then, the pressure sensitive adhesive tape adhered to the circuit forming surface of the semiconductor wafer is released, and a dicing tape is adhered to the back surface of the semiconductor wafer. Further, the semiconductor wafer is divided by dicing it into individual chips, and then the back surface of the chip is pressed by way of the dicing tape, thereby releasing the chips from the dicing tape.
    Type: Grant
    Filed: December 23, 2004
    Date of Patent: November 18, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Chuichi Miyazaki, Yoshiyuki Abe, Toshihide Uematsu, Minoru Kimura, Kazunari Suzuki, Masao Odagiri, Hideyuki Suga, Manabu Takata
  • Publication number: 20060150527
    Abstract: This invention provides flame-generated fine silica particles having an average particle size of 0.05 to 1 ?m, wherein a fractal structure parameter ?1 at length scales ranging from 50 nm to 150 nm and a fractal structure parameter ?2 at length scales ranging from 150 nm to 353 nm satisfy the following formulas (1) and (2): ?0.0068S+2.548??1??0.0068S+3.748??(1) ?0.0011S+1.158??2??0.0011S+2.058??(2) wherein S is a BET specific surface area (m2/g) of the fine silica particles, in the measurement of small-angle X-ray scattering. When used as a filler for a semiconductor-encapsulation resin or when used as a filler for a polishing agent or for a coating layer for ink jet papers, the fine silica particles are available at high content without substantial enhancement of the viscosity. Besides, when used as a filler for the resin, the fine silica particles improve the strength of the molding compound.
    Type: Application
    Filed: December 25, 2003
    Publication date: July 13, 2006
    Inventors: Masakazu Ohara, Minoru Kimura, Hiroo Aoki
  • Patent number: 7074515
    Abstract: Making a larger difference in water activity between electrodes elevates an output voltage of an electrochemical element. The electrochemical element includes a solid electrolyte membrane 5 made of a solid electrolyte and possessing a hydrogen ion conductivity, a first electrode 6 formed on one side of the solid electrolyte membrane 5 and functioning as a catalyst and possessing a hydrophilic property, and a second electrode 7 formed on the other side of the solid electrolyte membrane 5 and functioning as a catalyst and possessing a water-repellent property.
    Type: Grant
    Filed: August 6, 2002
    Date of Patent: July 11, 2006
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shiro Yamauchi, Minoru Kimura, Hirokazu Terauchi, Osamu Takai, Goro Yamauchi
  • Patent number: 7047107
    Abstract: There are provided a parameter storage part for storing monitor point information, a locus generation part for generating motions of the support, each joint point, and the like based on the movement command, a control point speed control part for obtaining speed of the control point such as the support, each joint point, and the like, a monitor point speed control part for obtaining speed of the monitor point generated from motion speed of the control point, and a motion command part for selecting the maximum speed among the speed of the control point and the speed of the monitor point to compare the maximum speed with the command speed and changing and controlling the speed of the control point to the command speed when the maximum speed exceeds the command speed.
    Type: Grant
    Filed: February 22, 2001
    Date of Patent: May 16, 2006
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Sachiyo Minoshima, Minoru Kimura, Hisako Kimura, Katsumi Kimura
  • Publication number: 20050260829
    Abstract: The reliability of a thin semiconductor device is to be improved. A tape having a ring affixed to an outer periphery thereof is affixed to a main surface of a semiconductor wafer, and, in this state, a back surface of the semiconductor wafer is subjected to grinding and polishing to thin the wafer. Thereafter, the semiconductor wafer is conveyed to a dicing apparatus in a state in which the tape with the ring is affixed to the wafer main surface without peeling of the tape, and dicing is performed from the back surface side of the semiconductor wafer to divide the wafer into individual semiconductor chips. With this method, handling of the thin semiconductor wafer by rear surface processing can be facilitated. Besides, the manufacturing process can be simplified because the replacement of the tape is not needed at the time of shift from rear surface processing to the dicing process.
    Type: Application
    Filed: May 3, 2005
    Publication date: November 24, 2005
    Inventors: Toshihide Uematsu, Chuichi Miyazaki, Yoshiyuki Abe, Minoru Kimura
  • Publication number: 20050230269
    Abstract: A nitrogen oxide decomposing element and a nitrogen oxide decomposing apparatus can perform a treatment at a relatively low temperature without using a material, which is suspected to have influence on the environment and human body, as an oxidant or a catalyst. There is proposed a nitrogen oxide decomposing element 1 including a conductive solid electrolyte film 2 for selectively allowing a hydrogen ion to pass through, a first electrode layer 3 made of an electronic conductivity base material and a catalyst for accelerating anodic oxidation, a second electrode layer 4 made of an electronic conductivity basematerialandacatalystforacceleratingcathodicreduction, and a platinum group catalyst 6 supported by a porous metal oxide 5 disposed to be adjacent to the second electrode layer 4.
    Type: Application
    Filed: September 26, 2003
    Publication date: October 20, 2005
    Applicants: MITSUBISHI DENKI KABUSHIKI KAISHA, Masato MACHIDA
    Inventors: Masato Machida, Shiro Yamauchi, Minoru Kimura, Shigeru Yamaji
  • Publication number: 20050142815
    Abstract: A technique capable of stably releasing chips from a dicing tape, includes grinding a back surface of a semiconductor wafer, while adhering a pressure sensitive adhesive tape to a circuit forming surface of the semiconductor wafer formed with an integrated circuit, to achieve a predetermined thickness and forcibly oxidizing the back surface of the semiconductor wafer. Then, the pressure sensitive adhesive tape adhered to the circuit forming surface of the semiconductor wafer is released, and a dicing tape is adhered to the back surface of the semiconductor wafer. Further, the semiconductor wafer is divided by dicing it into individual chips, and then the back surface of the chip is pressed by way of the dicing tape, thereby releasing the chips from the dicing tape.
    Type: Application
    Filed: December 23, 2004
    Publication date: June 30, 2005
    Inventors: Chuichi Miyazaki, Yoshiyuki Abe, Toshihide Uematsu, Minoru Kimura, Kazunari Suzuki, Masao Odagiri, Hideyuki Suga, Manabu Takata
  • Patent number: 6814122
    Abstract: The present invention provides a radial tire forming apparatus capable of being applied to the formation of a carcass band having a large folding length. On a housing for a rollover device of the tire forming apparatus, a plurality of sets of straight rail bearers are fixed at appropriate places, so that a frame provided with rails is advanced toward or retreated from a second forming point on the carcass forming former side by a cylinder fixed to the housing. The diameter of a first rollover ring is slightly smaller than the diameter of a second rollover ring. When the rollover rings are brought closest to each other, the cylindrical portions of the rings enter and lap on each other.
    Type: Grant
    Filed: May 23, 2002
    Date of Patent: November 9, 2004
    Assignee: Mitsubishi Heavy Industries, Ltd.
    Inventors: Minoru Kimura, Nobuhiko Irie, Yoshihiro Fukamachi