Patents by Inventor Minoru Kumagai

Minoru Kumagai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10243157
    Abstract: A thin film transistor array includes a substrate, a gate electrode formed on the substrate, a gate insulation film covering the gate electrode, a source electrode formed on the gate insulation film, a drain electrode formed on the gate insulation film, a semiconductor layer connected to the source electrode and the drain electrode, an interlayer insulation film formed on the drain electrode and the semiconductor layer, and a pixel electrode formed on the interlayer insulation film. The interlayer insulation film has a via hole that reaches a portion of the drain electrode, and the drain electrode has a liquid repellent coating on the portion positioned in the via hole.
    Type: Grant
    Filed: March 25, 2016
    Date of Patent: March 26, 2019
    Assignee: TOPPAN PRINTING CO., LTD.
    Inventors: Minoru Kumagai, Noriaki Ikeda
  • Publication number: 20160285019
    Abstract: A thin film transistor array includes a substrate, a gate electrode formed on the substrate, a gate insulation film covering the gate electrode, a source electrode formed on the gate insulation film, a drain electrode formed on the gate insulation film, a semiconductor layer connected to the source electrode and the drain electrode, an interlayer insulation film formed on the drain electrode and the semiconductor layer, and a pixel electrode formed on the interlayer insulation film. The interlayer insulation film has a via hole that reaches a portion of the drain electrode, and the drain electrode has a liquid repellent coating on the portion positioned in the via hole.
    Type: Application
    Filed: March 25, 2016
    Publication date: September 29, 2016
    Applicant: TOPPAN PRINTING CO., LTD.
    Inventors: Minoru KUMAGAI, Noriaki IKEDA
  • Patent number: 8087962
    Abstract: A manufacturing method of a display apparatus which comprises a plurality of display pixels including light emitting elements having a carrier transport layer includes first causing a surface of an electrode formed in a forming region of the plurality of display pixels by being enclosed by a partition wall which is provided on a substrate to have a lyophilic characteristic, making a surface of the partition wall have a repellency characteristic and second causing the surface of the electrode to have the lyophilic characteristic again by carrying out a plasma treatment in an inert gas atmosphere.
    Type: Grant
    Filed: September 16, 2008
    Date of Patent: January 3, 2012
    Assignee: Casio Computer Co., Ltd.
    Inventor: Minoru Kumagai
  • Patent number: 8049413
    Abstract: A bank for defining the regions in which pixels are formed has a stacked structure including: a base layer on the low level which also serves as an interlayer insulating film between the pixel forming regions; a middle bank layer on the middle level which serves to improve the fixation of an organic compound material (i.e., improve the uniformity of the film thickness of a positive hole transporting layer and an electron-transporting light emitting layer) in forming an organic EL layer; and a bank metal layer on the upper level which is made of a conductive material and serves also as a common voltage line (cathode line).
    Type: Grant
    Filed: December 15, 2009
    Date of Patent: November 1, 2011
    Assignee: Casio Computer Co., Ltd.
    Inventor: Minoru Kumagai
  • Patent number: 7981484
    Abstract: An object of the present invention is to provide a display device that has carrier transport layer with relatively uniform film thickness, at pixel forming region of display pixel, and a manufacturing thereof. A manufacturing method of a display device provided with a luminescent element that has a carrier transport layer includes a liquid repellent film forming step to form a liquid repellent film on a surface of a plurality of barrier walls provided on a substrate; a coating step to coat a carrier transport material containing acidic solution that contains carrier transport layer material on a pixel electrode arranged in between the plurality of barrier walls; and a drying step to dry the carrier transport material containing acidic solution under inert gas atmosphere.
    Type: Grant
    Filed: September 19, 2006
    Date of Patent: July 19, 2011
    Assignee: Casio Computer Co., Ltd.
    Inventor: Minoru Kumagai
  • Patent number: 7892059
    Abstract: A manufacturing method of a display device the method comprising a step of etching a surface of a partitioning wall formed on a substrate around region where a display pixel is formed.
    Type: Grant
    Filed: May 10, 2007
    Date of Patent: February 22, 2011
    Assignee: Casio Computer Co., Ltd.
    Inventor: Minoru Kumagai
  • Patent number: 7889488
    Abstract: A lock unit used for an electronic apparatus that includes a foldable and unfoldable housing that has a first surface that is foldable, and a second surface orthogonal to the first surface includes a lock member that locks the housing in a folded state, an operation member that moves the lock member and releases a lock of the housing by the lock member, and a transmission mechanism that transmits a driving force applied to the operation member to the lock member by changing an operating direction of the operation member to another direction, and moves the lock member in the other direction, wherein the operation member is provided on the second surface, and an operating direction of the operation member is a first direction perpendicular to the second surface, the lock member projecting in a second direction orthogonal to the first surface, and a moving direction of the lock member being a third direction orthogonal to the first and second directions.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: February 15, 2011
    Assignee: Fujitsu Limited
    Inventors: Minoru Kumagai, Ikki Tatsukami, Kazuo Kobayashi, Wataru Tanaka, Kaigo Tanaka
  • Patent number: 7871837
    Abstract: A display panel manufacturing method according to one aspect of the present invention comprises: patterning a plurality of pixel electrodes on a panel to be arrayed in a matrix; forming an interconnection made of a metal between the pixel electrodes; coating a surface of the interconnection with a liquid repellent conductive layer; and forming an organic compound layer by applying an organic compound-containing solution to the electrodes.
    Type: Grant
    Filed: June 3, 2009
    Date of Patent: January 18, 2011
    Assignee: Casio Computer Co., Ltd.
    Inventors: Satoru Shimoda, Tomoyuki Shirasaki, Jun Ogura, Minoru Kumagai
  • Patent number: 7830084
    Abstract: A display panel including a plurality of pixels. Each pixel includes: a light emitting element; a pixel circuit having a driving transistor connected to the light emitting element in series; a data line to which a data current is supplied through the pixel circuit; a scanning line for selecting the pixel circuit; a first insulation film to cover the data line; and a second insulation film made of a material different from the first insulation film, to cover the data line and the first insulation film, wherein the following expression is satisfied. C total 20 ? ? 0 ? ? a ? ? b ? a ? D b + ? b ? D a ? C total 5 Ctotal: parasitic capacitance of whole path to data line through pixel circuit; ?0: vacuum dielectric constant; ?a: relative dielectric constant of first insulation film; Da: first insulation film thickness; ?b: relative dielectric constant of second insulation film; Db: second insulation film thickness.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: November 9, 2010
    Assignee: Casio Computer Co., Ltd.
    Inventors: Tomoyuki Shirasaki, Minoru Kumagai, Hiroyasu Yamada, Tsuyoshi Ozaki, Jun Ogura
  • Publication number: 20100172074
    Abstract: A lock unit used for an electronic apparatus that includes a foldable and unfoldable housing that has a first surface that is foldable, and a second surface orthogonal to the first surface includes a lock member that locks the housing in a folded state, an operation member that moves the lock member and releases a lock of the housing by the lock member, and a transmission mechanism that transmits a driving force applied to the operation member to the lock member by changing an operating direction of the operation member to another direction, and moves the lock member in the other direction, wherein the operation member is provided on the second surface, and an operating direction of the operation member is a first direction perpendicular to the second surface, the lock member projecting in a second direction orthogonal to the first surface, and a moving direction of the lock member being a third direction orthogonal to the first and second directions.
    Type: Application
    Filed: December 29, 2009
    Publication date: July 8, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Minoru Kumagai, Ikki Tatsukami, Kazuo Kobayashi, Wataru Tanaka, Kaigo Tanaka
  • Publication number: 20100090933
    Abstract: A bank for defining the regions in which pixels are formed has a stacked structure including: a base layer on the low level which also serves as an interlayer insulating film between the pixel forming regions; a middle bank layer on the middle level which serves to improve the fixation of an organic compound material (i.e., improve the uniformity of the film thickness of a positive hole transporting layer and an electron-transporting light emitting layer) in forming an organic EL layer; and a bank metal layer on the upper level which is made of a conductive material and serves also as a common voltage line (cathode line).
    Type: Application
    Filed: December 15, 2009
    Publication date: April 15, 2010
    Applicant: CASIO COMPUTER CO., LTD.
    Inventor: Minoru KUMAGAI
  • Patent number: 7695759
    Abstract: A bank for defining the regions in which pixels are formed has a stacked structure including: a base layer on the low level which also serves as an interlayer insulating film between the pixel forming regions; a middle bank layer on the middle level which serves to improve the fixation of an organic compound material (i.e., improve the uniformity of the film thickness of a positive hole transporting layer and an electron-transporting light emitting layer) in forming an organic EL layer; and a bank metal layer on the upper level which is made of a conductive material and serves also as a common voltage line (cathode line).
    Type: Grant
    Filed: May 8, 2007
    Date of Patent: April 13, 2010
    Assignee: Casio Computer Co., Ltd.
    Inventor: Minoru Kumagai
  • Patent number: 7665774
    Abstract: A lock unit used for an electronic apparatus that includes a foldable and unfoldable housing that has a first surface that is foldable, and a second surface orthogonal to the first surface includes a lock member that locks the housing in a folded state, an operation member that moves the lock member and releases a lock of the housing by the lock member, and a transmission mechanism that transmits a driving force applied to the operation member to the lock member by changing an operating direction of the operation member to another direction, and moves the lock member in the other direction, wherein the operation member is provided on the second surface, and an operating direction of the operation member is a first direction perpendicular to the second surface, the lock member projecting in a second direction orthogonal to the first surface, and a moving direction of the lock member being a third direction orthogonal to the first and second directions.
    Type: Grant
    Filed: October 15, 2007
    Date of Patent: February 23, 2010
    Assignee: Fujitsu Limited
    Inventors: Minoru Kumagai, Ikki Tatsukami, Kazuo Kobayashi, Wataru Tanaka, Kaigo Tanaka
  • Publication number: 20090315027
    Abstract: A manufacturing method of a light emitting device in which at least one carrier transporting layer is interposed between a first electrode and a second electrode, includes: removing a surface layer of a partition that surrounds a periphery of at least one side of the first electrode by a thickness of 50 nm or more; and forming the carrier transporting layer on the first electrode, the carrier transporting layer being in contact with the partition and containing a transition metal oxide.
    Type: Application
    Filed: June 18, 2009
    Publication date: December 24, 2009
    Applicant: Casio Computer Co., Ltd.
    Inventors: Takashi KIDU, Minoru Kumagai
  • Publication number: 20090239321
    Abstract: A transistor array substrate includes a plurality of driving transistors which are arrayed in a matrix on a substrate. The driving transistor has a gate, a source, a drain, and a gate insulating film inserted between the gate, and the source and drain. A plurality of signal lines are patterned together with the gates of the driving transistors and arrayed to run in a predetermined direction on the substrate. A plurality of supply lines are patterned together with the sources and drains of the driving transistors and arrayed to cross the signal lines via the gate insulating film. The supply line is electrically connected to one of the source and the drain of the driving transistor. A plurality of feed interconnections are formed on the supply lines along the supply lines, respectively.
    Type: Application
    Filed: June 3, 2009
    Publication date: September 24, 2009
    Applicant: Casio Computer Co., Ltd.
    Inventors: Satoru SHIMODA, Tomoyuki Shirasaki, Jun Ogura, Minoru Kumagai
  • Publication number: 20090220679
    Abstract: A method of manufacturing a display apparatus including an optical element having an optical material layer between a first electrode and a second electrode which are formed on a substrate, includes an aligning step of making the substrate oppose a plate which has a wettability changeable layer and to which a droplet of an optical material containing liquid sticks in accordance with a pattern based on a difference in wettability. The substrate and the plate are aligned with each other, and the droplet is bring into contact with the substrate to transfer the droplet to the substrate side, thereby forming the optical material layer.
    Type: Application
    Filed: March 16, 2009
    Publication date: September 3, 2009
    Applicant: Casio Computer Co., Ltd.
    Inventors: Minoru Kumagai, Tomoyuki Shirasaki
  • Patent number: 7580265
    Abstract: A heat sink that radiates n exoergic circuit elements mounted on a circuit board includes a housing that has a heat-receiving surface that receives heat from the n exoergic circuit elements, and n+2 fixture parts to each of which a fixture member is attachable, each fixture member compressively fixing the housing onto the circuit board, wherein n is equal to or greater than 2, the heat sink is used to commonly radiate the n exoergic circuit elements, and a line that connects two fixture members to each other among n+2 fixture members passes between two centers of gravity of two adjacent exoergic circuit elements.
    Type: Grant
    Filed: October 15, 2007
    Date of Patent: August 25, 2009
    Assignee: Fujitsu Limited
    Inventors: Minoru Kumagai, Ikki Tatsukami, Takashi Iijima
  • Patent number: 7573068
    Abstract: A transistor array substrate includes a plurality of driving transistors which are arrayed in a matrix on a substrate. The driving transistor has a gate, a source, a drain, and a gate insulating film inserted between the gate, and the source and drain. A plurality of signal lines are patterned together with the gates of the driving transistors and arrayed to run in a predetermined direction on the substrate. A plurality of supply lines are patterned together with the sources and drains of the driving transistors and arrayed to cross the signal lines via the gate insulating film. The supply line is electrically connected to one of the source and the drain of the driving transistor. A plurality of feed interconnections are formed on the supply lines along the supply lines, respectively.
    Type: Grant
    Filed: September 21, 2005
    Date of Patent: August 11, 2009
    Assignee: Casio Computer Co., Ltd.
    Inventors: Satoru Shimoda, Tomoyuki Shirasaki, Jun Ogura, Minoru Kumagai
  • Publication number: 20090070995
    Abstract: A manufacturing method of a display apparatus which comprises a plurality of display pixels including light emitting elements having a carrier transport layer includes first causing a surface of an electrode formed in a forming region of the plurality of display pixels by being enclosed by a partition wall which is provided on a substrate to have a lyophilic characteristic, making a surface of the partition wall have a repellency characteristic and second causing the surface of the electrode to have the lyophilic characteristic again by carrying out a plasma treatment in an inert gas atmosphere.
    Type: Application
    Filed: September 16, 2008
    Publication date: March 19, 2009
    Applicant: Casio Computer Co., Ltd.
    Inventor: Minoru KUMAGAI
  • Patent number: 7440267
    Abstract: The present invention relates to various types of electronic apparatus having a folding structure via hinges and aims to help further enrich and compact functions. The apparatus includes: a first enclosure having a circuit component; a hinge unit rotatably connected to the first enclosure via a hinge; and a second enclosure having a circuit component and connected to the first enclosure via the hinge unit, in which the hinge unit has a circuit component.
    Type: Grant
    Filed: November 8, 2005
    Date of Patent: October 21, 2008
    Assignee: Fujitsu Limited
    Inventors: Ikki Tatsukami, Minoru Kumagai, Yutaka Satou, Takashi Iijima, Tadashi Kikkawa