Abstract: The magnetic pole position of the rotor is estimated with high accuracy at the initial start of a three-phase motor of the sensorless system. Semiconductor device for driving and controlling the three-phase motor of the sensorless system have a detector connected to the three-phase output nodes of the inverter circuit and the virtual neutral point (or neutral point), and detecting a voltage generated in the output node of the non-energized phase of the three-phase. Controller applies the initial drive voltage by the inverter circuit to any two phases of the three-phase motor based on the estimated position of the magnetic pole of the rotor in the stop state. Controller estimates the position of the rotor based on a difference voltage detected by the detector in a driving voltage applying period and a regeneration period immediately after or immediately before the driving voltage applying period.

Abstract: The semiconductor device includes: a current detection circuit configured to detect a current flowing through a three-phase motor by driving of a drive circuit; and a controller configured to control the drive circuit, based on the detected current. The controller is configured to control, when the three-phase motor is stationary, an energization pattern in such a way that a wave detection current sequentially flows from the drive circuit to each phase of the three-phase motor, to obtain, from the wave detection current detected by the current detection circuit, a first, a second and a third interphase current differences, each of which is a difference among wave detection currents flowing in directions opposite to one another, to determine the energization pattern based on a magnitude relationship among the first, the second and the third interphase current differences.

Abstract: A gate drive semiconductor device includes: external terminals to which PWM control signals are supplied; external terminals outputting a drive signal for driving a three-phase BLDC motor; external terminals to which the counter electromotive voltage generated by driving the three-phase BLDC motor is supplied; a zero-cross determination unit generating an interrupt signal indicating timing at which the counter electromotive voltage intersects with a midpoint potential of the three-phase BLDC motor based on the PWM control signal and the counter electromotive voltage; and an external terminal outputting the interrupt signal.

Abstract: The magnetic pole position of the rotor is estimated with high accuracy at the initial start of a three-phase motor of the sensorless system. Semiconductor device for driving and controlling the three-phase motor of the sensorless system have a detector connected to the three-phase output nodes of the inverter circuit and the virtual neutral point (or neutral point), and detecting a voltage generated in the output node of the non-energized phase of the three-phase. Controller applies the initial drive voltage by the inverter circuit to any two phases of the three-phase motor based on the estimated position of the magnetic pole of the rotor in the stop state. Controller estimates the position of the rotor based on a difference voltage detected by the detector in a driving voltage applying period and a regeneration period immediately after or immediately before the driving voltage applying period.

Abstract: A gate drive semiconductor device includes: external terminals to which PWM control signals are supplied; external terminals outputting a drive signal for driving a three-phase BLDC motor; external terminals to which the counter electromotive voltage generated by driving the three-phase BLDC motor is supplied; a zero-cross determination unit generating an interrupt signal indicating timing at which the counter electromotive voltage intersects with a midpoint potential of the three-phase BLDC motor based on the PWM control signal and the counter electromotive voltage; and an external terminal outputting the interrupt signal.

Abstract: The phase error detection unit PHED detects the phase error PERR between the phase of the BEMF and the phase of the phase switching signal COMM (masking signal MSK) at each of a plurality of detection timings that become the zero crossing timings of the BEMF in the mechanical angular cycle. The PI compensator PICPa has a plurality of cycle setting registers REGN 0_0 to REGN 3_5 for each of a plurality of detection timings, and while switching the registers for each detection timing, the PI compensator determines the cycle setting value NCNTS for bringing the inputted phase error PERR close to zero by reflecting the previous cycle setting value NCNT stored in the register. The clock generation unit CGEN sequentially controls the phase switching signal COMM based on the cycle setting value NCNTS.

Abstract: An output control unit controls a drive terminal for a BEMF detection object phase to a high-impedance state in a mask term. A BEMF detection unit detects a voltage of the drive terminal for the detection object phase when a center tap voltage is set as a reference as BEMF in a PWM on-term for remaining two phases per PWM period in the mask term and asserts a zero-crossing signal when the voltage is reduced to zero. A PWM fixing unit fixes the remaining two phases to the PWM on-terms in a first term from a predetermined timing after an amplitude level of BEMF becomes smaller than a BEMF threshold amplitude to assertion of the zero-crossing signal. The BEMF detection unit continuously detects BEMF in the first term.

Abstract: The phase error detection unit PHED detects the phase error PERR between the phase of the BEMF and the phase of the phase switching signal COMM (masking signal MSK) at each of a plurality of detection timings that become the zero crossing timings of the BEMF in the mechanical angular cycle. The PI compensator PICPa has a plurality of cycle setting registers REGN 0_0 to REGN 3_5 for each of a plurality of detection timings, and while switching the registers for each detection timing, the PI compensator determines the cycle setting value NCNTS for bringing the inputted phase error PERR close to zero by reflecting the previous cycle setting value NCNT stored in the register. The clock generation unit CGEN sequentially controls the phase switching signal COMM based on the cycle setting value NCNTS.

Abstract: A PWM modulation circuit controls low-side transistors of three phases to all be in an ON state when a brake current flows; controls, in a period in which a brake current flows in a first direction in one phase, a transistor for sensing in that one phase to be in an ON state; and controls, in a period in which a brake current flows in the first direction in two phases, transistors for three phases to be in an OFF state. When the brake current is to flow, sense-phase control circuits for the three phases control a transistor for sensing, in a phase in which the brake current flows in a sink direction, to be into an ON state, and controls the transistor for sensing in a phase in which the brake current flows in an opposite direction, to be into an OFF state.

Abstract: An output control unit controls a drive terminal for a BEMF detection object phase to a high-impedance state in a mask term. A BEMF detection unit detects a voltage of the drive terminal for the detection object phase when a center tap voltage is set as a reference as BEMF in a PWM on-term for remaining two phases per PWM period in the mask term and asserts a zero-crossing signal when the voltage is reduced to zero. A PWM fixing unit fixes the remaining two phases to the PWM on-terms in a first term from a predetermined timing after an amplitude level of BEMF becomes smaller than a BEMF threshold amplitude to assertion of the zero-crossing signal. The BEMF detection unit continuously detects BEMF in the first term.

Abstract: A motor driving device and a motor system that can reduce a torque ripple of a motor are provided. The current control loop detects a drive current of the motor, detects an error between the detected value of the drive current and a current indication value as a target value of the drive current, and determines the duty of the PWM signal reflecting the error concerned. The back EMF phase detector detects the phase of a back electromotive force of each phase in the motor. The torque correction unit calculates a first torque correction coefficient of a periodic function based on the phase variations in the three phases of the back electromotive force, and corrects the current indication value superimposing the first torque correction coefficient on the current indication value.

Abstract: A PWM modulation circuit controls low-side transistors of three phases (u, v, and w) all to be into an ON state, when a brake current flows, controls, in a period in which a brake current flows in one phase, a transistor for sensing (u, v, and w) of this one phase to be into an ON state, and controls, in a period of two phases, the transistor for sensing (u, v, and w) of three phases to be into an OFF state. When the brake current is to flow, sense-phase control circuits of three phases controls a transistor for sensing (u, v, and w), in a phase in which the brake current is in a sink direction, to be into an ON state, and controls the transistor for sensing (u, v, and w) in a phase in which it is in an opposite direction, to be into an OFF state.

Abstract: The phase of a drive current of a motor is optimized. The phase arithmetic unit PHCAL calculates a drive voltage phase ?drv to converge the phase difference between the reference voltage phase ?bemf and the reference current phase ?i to zero based on a prescribed arithmetic expression. The phase correction unit PHCP determines the phase ?drvR after the correction by adding a correction value to the phase ?drv, and the magnitude of the correction value is updated by a feedback control so as to converge to a prescribed value the phase difference between the reference voltage phase ?bemf and the reference current phase ?i which are inputted. A PWM controller shifts an energization control timing synchronized with the reference voltage phase ?bemf based on the corrected phase ?drvR, and generates the PWM signal for controlling the drive voltage to a sine wave shape.

Abstract: A control device is provided which can perform a retraction operation of a head included in a disk storage device with lower power consumption. The control device of the disk storage device includes a control unit that controls a motor and retracts the head from over a disk to a ramp mechanism when power supply is shut down, an acquisition unit that acquires information related to a moving distance of the head that retracts to the ramp mechanism, and a calculation unit that calculates the moving distance of the head based on the information acquired by the acquisition unit. The control unit switches an operation of the motor from a first retract operation to a second retract operation when determining that the head reaches a first position after passing through an inclined surface of the ramp mechanism based on the moving distance calculated by the calculation unit.

Abstract: A motor driving device and a motor system that can reduce a torque ripple of a motor are provided. The current control loop detects a drive current of the motor, detects an error between the detected value of the drive current and a current indication value as a target value of the drive current, and determines the duty of the PWM signal reflecting the error concerned. The back EMF phase detector detects the phase of a back electromotive force of each phase in the motor. The torque correction unit calculates a first torque correction coefficient of a periodic function based on the phase variations in the three phases of the back electromotive force, and corrects the current indication value superimposing the first torque correction coefficient on the current indication value.

Abstract: A control device is provided which can perform a retraction operation of a head included in a disk storage device with lower power consumption. The control device of the disk storage device includes a control unit that controls a motor and retracts the head from over a disk to a ramp mechanism when power supply is shut down, an acquisition unit that acquires information related to a moving distance of the head that retracts to the ramp mechanism, and a calculation unit that calculates the moving distance of the head based on the information acquired by the acquisition unit. The control unit switches an operation of the motor from a first retract operation to a second retract operation when determining that the head reaches a first position after passing through an inclined surface of the ramp mechanism based on the moving distance calculated by the calculation unit.

Abstract: There are provided a motor drive device and a motor system that can reduce the torque ripple of a motor. An SPM drive unit includes a plurality of high side transistors and low side transistors coupled to drive terminals of multiple phases respectively, and applies drive voltages to the drive terminals, using a PWM signal. A back electromotive force voltage phase detection unit detects each of back electromotive force voltage phases of the multiple phases. A drive voltage phase generation unit determines one of drive voltage phases in each of the multiple phases at the time of applying the drive voltages so that each of drive current phases of the multiple phases has a phase variation opposite in direction and equal to each of relative phase variations of the back electromotive force voltage phases of the multiple phases.

Abstract: A transistor includes: a piezoresistor through which carriers conduct; a source that injects the carriers into the piezoresistor; a drain that receives the carriers from the piezoresistor; a piezoelectric material that is located so as to surround the piezoresistor and applies a pressure to the piezoresistor; and a gate that applies a voltage to the piezoelectric material so that the piezoelectric material applies a pressure to the piezoresistor.

Abstract: A power supply device is responsive to load changes. The power supply device includes a switch control circuit, a charge control circuit, and a discharge control circuit. The switch control circuit controls switches so that electrical power is charged into an inductor, discharged from the inductor, and distributed to first and second capacitors in a time-division manner based on a switching cycle. The charge control circuit controls the amount of electrical power to be charged into the inductor based on a first amount of error between a first output power supply voltage and its target value and a second amount of error between a second output power supply voltage and its target value. The discharge control circuit controls a distribution ratio at which the electrical power discharged from the inductor is distributed to the first and second capacitors based on the ratio between the first and second amounts of error.

Abstract: The phase of a drive current of a motor is optimized. The phase arithmetic unit PHCAL calculates a drive voltage phase ?drv to converge the phase difference between the reference voltage phase ?bemf and the reference current phase ?i to zero based on a prescribed arithmetic expression. The phase correction unit PHCP determines the phase ?drvR after the correction by adding a correction value to the phase ?drv, and the magnitude of the correction value is updated by a feedback control so as to converge to a prescribed value the phase difference between the reference voltage phase ?bemf and the reference current phase ?i which are inputted. A PWM controller shifts an energization control timing synchronized with the reference voltage phase ?bemf based on the corrected phase ?drvR, and generates the PWM signal for controlling the drive voltage to a sine wave shape.