Patents by Inventor Minoru Miyazaki
Minoru Miyazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6166414Abstract: An electronic circuit formed on an insulating substrate and having thin-film transistors (TFTs) comprising semiconductor layers. The thickness of the semiconductor layers is less than 1500 .ANG., e.g., between 100 and 750 .ANG.. A first layer consisting mainly of titanium and nitrogen is formed on the semiconductor layer. A second layer consisting aluminum is formed on top of the first layer. The first and second layers are patterned into conductive interconnects. The bottom surface of the second layer is substantially totally in intimate contact with the first layer. The interconnects have good contacts with the semiconductor layer.Type: GrantFiled: August 25, 1999Date of Patent: December 26, 2000Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Minoru Miyazaki, Akane Murakami, Baochun Cui, Mutsuo Yamamoto
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Patent number: 6031290Abstract: An electronic circuit formed on an insulating substrate and having thin-film transistors (TFTs) comprising semiconductor layers. The thickness of the semiconductor layers is less than 1500 .ANG., e.g., between 100 and 750 .ANG.. A first layer consisting mainly of titanium and nitrogen is formed on the semiconductor layer. A second layer consisting aluminum is formed on top of the first layer. The first and second layers are patterned into conductive interconnects. The bottom surface of the second layer is substantially totally in intimate contact with the first layer. The interconnects have good contacts with the semiconductor layer.Type: GrantFiled: March 13, 1998Date of Patent: February 29, 2000Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Minoru Miyazaki, Akane Murakami, Baochun Cui, Mutsuo Yamamoto
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Patent number: 5830786Abstract: A process for fabricating an electronic circuit by oxidizing the surroundings of a metallic interconnection such as of aluminum, tantalum, and titanium, wherein anodic oxidation is effected at a temperature not higher than room temperature, preferably, at 10.degree. C. or lower, and more preferably, at 0.degree. C. or lower. The surface oxidation rate of a metallic interconnection can be maintained constant to provide a surface free of irregularities.Type: GrantFiled: May 28, 1996Date of Patent: November 3, 1998Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hongyong Zhang, Hideki Uochi, Shunpei Yamazaki, Yasuhiko Takemura, Minoru Miyazaki, Akane Murakami, Toshimitsu Konuma, Akira Sugawara, Yukiko Uehara
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Patent number: 5808315Abstract: According to a transparent conductive film forming method, after an ITO (Indium Tin Oxide) thin film is formed at room temperature by a sputtering method, an annealing treatment is conducted on the film under hydrogen atmosphere at a suitable temperature such as a temperature higher than 200.degree. C.Type: GrantFiled: December 19, 1996Date of Patent: September 15, 1998Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Akane Murakami, Baochun Cui, Minoru Miyazaki
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Patent number: 5804878Abstract: An electronic circuit formed on an insulating substrate and having thin-film transistors (TFTs) comprising semiconductor layers. The thickness of the semiconductor layers is less than 1500 .ANG., e.g., between 100 and 750 .ANG.. A first layer consisting mainly of titanium and nitrogen is formed on the semiconductor layer. A second layer consisting aluminum is formed on top of first layer. The first and second layers are patterned into conductive interconnects. The bottom surface of the second layer is substantially totally in intimate contact with the first layer. The interconnects have good contacts with the semiconductor layer.Type: GrantFiled: April 24, 1996Date of Patent: September 8, 1998Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Minoru Miyazaki, Akane Murakami, Baochun Cui, Mutsuo Yamamoto
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Patent number: 5677240Abstract: According to a transparent conductive film forming method, after an ITO (Indium Tin Oxide) thin film is formed at room temperature by a sputtering method, an annealing treatment is conducted on the film under hydrogen atmosphere at a suitable temperature such as a temperature higher than 200.degree. C.Type: GrantFiled: May 26, 1995Date of Patent: October 14, 1997Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Akane Murakami, Baochun Cui, Minoru Miyazaki
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Patent number: 5623157Abstract: An electronic circuit formed on an insulating substrate and having thin-film transistors (TFTs) comprising semiconductor layers. The thickness of the semiconductor layers is less than 1500 .ANG., e.g., between 100 and 750 .ANG.. A first layer consisting mainly of titanium and nitrogen is formed on the semiconductor layer. A second layer consisting aluminum is formed on top of the first layer. The first and second layers are patterned into conductive interconnects. The bottom surface of the second layer is substantially totally in intimate contact with the first layer. The interconnects have good contacts with the semiconductor layer.Type: GrantFiled: June 7, 1995Date of Patent: April 22, 1997Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Minoru Miyazaki, Akane Murakami, Baochun Cui, Mutsuo Yamamoto
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Patent number: 5580800Abstract: A thin film transistor according to this invention has a gate electrode comprising a lower layer of aluminum of a high purity of over 99.5% and an upper layer of aluminum containing over 0.5% silicon. Alternatively, it has a gate electrode made by adding a IIIa group element to a IIIb group element. Residues produced by the etching of the silicon-containing aluminum gate electrode are etched with a mixture solution of hydrofluoric acid, nitric acid and acetic acid. After contact holes have been formed in an interlayer insulating film, laser annealing is carried out, and metal electrodes are formed in the contact holes thereafter.Type: GrantFiled: March 15, 1994Date of Patent: December 3, 1996Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hongyong Zhang, Yasuhiko Takemura, Hideki Uochi, Itaru Koyama, Minoru Miyazaki, Akane Murakami, Toshimitsu Konuma, Akira Sugawara, Yukiko Uehara
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Patent number: 5487370Abstract: To save energy and reduce pollution by exerting magnetic fields on fuel oil to facilitate to convert oil particles into minute particles.Type: GrantFiled: January 25, 1995Date of Patent: January 30, 1996Assignee: Atsushi MakiInventor: Minoru Miyazaki
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Patent number: 5353140Abstract: A liquid crystal display of the chiral smectic type is caused to have grey scales, by applying a voltage of an intermediate level to the liquid crystal. Within each picture element of the display, there are a number of domains of the liquid crystal layer, some being transparent while the other being opaque rendering grey tone to the picture element.Type: GrantFiled: November 30, 1992Date of Patent: October 4, 1994Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Takashi Inujima, Toshimitsu Konuma, Toshiji Hamatani, Akira Mase, Mitsunori Sakama, Minoru Miyazaki, Kaoru Koyanagi, Toshiharu Yamaguchi
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Patent number: 5196954Abstract: A liquid crystal display of the chiral smectic type is caused to have grey scales, by applying a voltage of an intermediate level to the liquid crystal. Within each picture element of the display, there are a number of domains of the liquid crystal layer, some being transparent while the other being opaque rendering grey tone to the picture element.Type: GrantFiled: September 12, 1988Date of Patent: March 23, 1993Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Takashi Inujima, Toshimitsu Konuma, Toshiji Hamatani, Akira Mase, Mitsunori Sakama, Minoru Miyazaki, Kaoru Koyanagi, Toshiharu Yamaguchi
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Patent number: 5036794Abstract: A CVD apparatus in which a reaction chamber includes a pair of electrodes which define a plasma generating space therebetween. A metallic enclosure surrounds the plasma generating space thereby preventing plasma which has been produced within the space from escaping. The enclosure can be utilized to support one or more substrates to be coated.Type: GrantFiled: March 23, 1990Date of Patent: August 6, 1991Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Mamoru Tashiro, Minoru Miyazaki, Mitsunori Sakama, Takeshi Fukada
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Patent number: 4936251Abstract: A vapor phase reaction apparatus includes a reaction chamber defined by first and second walls fixed opposite each other. Third and fourth walls are introduced into the reaction chamber already having affixed to them a substrate for deposition. A reactive gas is introduced into the reaction chamber for chemical vapor deposition onto the substrate.Type: GrantFiled: April 22, 1985Date of Patent: June 26, 1990Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Mamoru Tashiro, Minoru Miyazaki, Mitsunori Sakama, Takeshi Fukada
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Patent number: 4861143Abstract: A liquid crystal display of the chiral smectic type is caused to have grey scales, by applying a voltage of an intermediate level to the liquid crystal. Within each picture element of the display, there are a number of domains of the liquid crystal layer, some being transparent while the other being opaque rendering grey tone to the picture element.Type: GrantFiled: December 2, 1987Date of Patent: August 29, 1989Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Takashi Inujima, Toshimitsu Konuma, Toshiji Hamatani, Akira Mase, Mitsunori Sakama, Minoru Miyazaki, Kaoru Koyanagi, Toshiharu Yamaguchi
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Patent number: 4855805Abstract: The present invention provides a nonlinear semiconductor element which has a V-I characteristic of excellent origin symmetry and a liquid crystal display panel which employs such nonlinear semiconductor element. The nonlinear semiconductor has an n-i-n, n-i-p-i-n, or p-i-n-i-p type structure. The i-type semiconductor layer is intentionally doped with boron, which acts to make the i-type semiconductor layer more intrinsic.Type: GrantFiled: June 3, 1988Date of Patent: August 8, 1989Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Akira Mase, Toshimitsu Konuma, Minoru Miyazaki, Mitsunori Sakama, Takashi Inushima
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Patent number: 4844588Abstract: A method for manufacturing a liquid crystal device including forming a semiconductor layer on a first substrate and an underlying conductive layer; separating the semiconductor layer and the underlying conductive layer into the elements of an array by removing the parts of the semiconductor and the conductive layer between the elements; insulating the side surfaces of the elements of said array; forming an overlying conductive layer on the first substrate over the array; removing the conductive layer other than at least one strip extending over a part of each surface of the elements arranged in a line, together with the underlying semiconductor layer whereby parts of the separated underlying conductors are exposed in the form of a plurality of first electrodes; and mating the first substrate to a second substrate having a plurality of second electrodes corresponding to the first electrodes, with a liquid crystal layer in between.Type: GrantFiled: January 25, 1988Date of Patent: July 4, 1989Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Takashi Inushima, Akira Mase, Toshimitsu Konuma, Minoru Miyazaki, Mitsunori Sakama
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Patent number: 4799776Abstract: The liquid crystal display according to this invention comprises a liquid crystal cell having a pair of substrates with faced insides which are provided with electrodes, ferroelectric liquid crystal with a chiral smectic C phase in between said substrates and a polarizing plate on the light incidence side. One of said electrodes is a relfective electrode. The display is utilized with microcomputers, word processors, television or so on, and wherein, due to a small number of parts, the absorption loss of light is small and a reflective plate is prevented from being oxided and therefore degraded in reflection index, since it is not exposed to air.Type: GrantFiled: March 2, 1987Date of Patent: January 24, 1989Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Takashi Inujima, Akira Mase, Toshimitsu Konuma, Mitsunori Sakama, Toshiji Hamatani, Minoru Miyazaki, Kaoru Koyanagi, Toshiharu Yamaguchi
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Patent number: 4744862Abstract: A method of manufacturing a liquid crystal display panel including preparing a first substrate member by forming a first conductive layer serving as a first electrode on a first substrate having an insulating surface; forming a first non-single-crystal semiconductor layer laminate layer on the first substrate member where the forming of the first non-single-crystal semiconductor laminate member includes forming at least a first non-single-crystal semiconductor of P (or N) type on the substrate, forming an i-type second non-single-crystal semiconductor layer on the first non-single-crystal semiconduictor layer, the i-type layer containing an additive selected from the group consisting of carbon, nitrogen, oxygen, boron, and mixtures thereof, and forming a third non-single-crystal semiconductor layer of P (or N) type on the i-type second non-single-crystal semiconductor layer; forming a second conductive layer serving as a second electrode in a pattern on the first non-single-crystal semiconductor layer laminatType: GrantFiled: January 2, 1987Date of Patent: May 17, 1988Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Akira Mase, Toshimitsu Konuma, Minoru Miyazaki, Mitsunori Sakama, Takashi Inushima
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Patent number: 4723508Abstract: A plasma CVD apparatus including a reaction chamber; a pair of electrodes disposed in the reaction chamber between which plasma discharge occurs; a substrate support maintained at a reference voltage; a vacuum pump for evacuating the reaction chamber; a first voltage supply for supplying a first alternating voltage to one of the electrodes; and a second voltage supply for supplying a second alternating voltage to the other of the electrodes where the second alternating voltage is out-of-phase with respect to the first alternating voltage.Type: GrantFiled: April 8, 1986Date of Patent: February 9, 1988Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Takashi Inushima, Minoru Miyazaki, Mitsunori Sakama
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Patent number: 4636401Abstract: An apparatus for conducting chemical vapor deposition reduced pressure, comprising: means for feeding reactive gases; a reaction vessel for depositing a film layer from the reactive gases by application of thermal energy, light energy or electric energy singly or in combination; an exhaust means for exhausting unnecessary reactive gases and unnecessary reaction products from the reaction vessel and for vacuumizing or reducing pressure of the reaction vessel, including a turbo molecular pump and a pressure control valve interposed between the reaction vessel and a roughing rotary pump; and a method of chemical vapor deposition using such apparatus.Type: GrantFiled: February 14, 1985Date of Patent: January 13, 1987Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Mamoru Tashiro, Minoru Miyazaki