Patents by Inventor Minoru Nakagawa
Minoru Nakagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230343578Abstract: A semiconductor device manufacturing method includes a step which prepares a wafer source and a supporting member, a supporting step which supports the wafer source by the supporting member, and a wafer separating step in which the wafer source is cut in a horizontal direction from a thickness direction intermediate portion of the wafer source to separate, from the wafer source, a wafer structure which includes the supporting member and a wafer cut away from the wafer source.Type: ApplicationFiled: August 30, 2021Publication date: October 26, 2023Applicant: ROHM CO., LTD.Inventor: Minoru NAKAGAWA
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Publication number: 20230187486Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type having a first main surface at one side and a second main surface at another side, a trench gate structure including a gate trench formed in the first main surface of the semiconductor layer, and a gate electrode embedded in the gate trench via a gate insulating layer, a trench source structure including a source trench formed deeper than the gate trench and across an interval from the gate trench in the first main surface of the semiconductor layer, a source electrode embedded in the source trench, and a deep well region of a second conductivity type formed in a region of the semiconductor layer along the source trench, a ratio of a depth of the trench source structure with respect to a depth of the trench gate structure being not less than 1.5 and not more than 4.Type: ApplicationFiled: February 6, 2023Publication date: June 15, 2023Inventors: Minoru NAKAGAWA, Yuki NAKANO, Masatoshi AKETA, Masaya UENO, Seigo MORI, Kenji YAMAMOTO
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Patent number: 11605707Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type having a first main surface at one side and a second main surface at another side, a trench gate structure including a gate trench formed in the first main surface of the semiconductor layer, and a gate electrode embedded in the gate trench via a gate insulating layer, a trench source structure including a source trench formed deeper than the gate trench and across an interval from the gate trench in the first main surface of the semiconductor layer, a source electrode embedded in the source trench, and a deep well region of a second conductivity type formed in a region of the semiconductor layer along the source trench, a ratio of a depth of the trench source structure with respect to a depth of the trench gate structure being not less than 1.5 and not more than 4.Type: GrantFiled: June 16, 2021Date of Patent: March 14, 2023Assignee: ROHM CO., LTD.Inventors: Minoru Nakagawa, Yuki Nakano, Masatoshi Aketa, Masaya Ueno, Seigo Mori, Kenji Yamamoto
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Publication number: 20210305363Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type having a first main surface at one side and a second main surface at another side, a trench gate structure including a gate trench formed in the first main surface of the semiconductor layer, and a gate electrode embedded in the gate trench via a gate insulating layer, a trench source structure including a source trench formed deeper than the gate trench and across an interval from the gate trench in the first main surface of the semiconductor layer, a source electrode embedded in the source trench, and a deep well region of a second conductivity type formed in a region of the semiconductor layer along the source trench, a ratio of a depth of the trench source structure with respect to a depth of the trench gate structure being not less than 1.5 and not more than 4.Type: ApplicationFiled: June 16, 2021Publication date: September 30, 2021Inventors: Minoru NAKAGAWA, Yuki NAKANO, Masatoshi AKETA, Masaya UENO, Seigo MORI, Kenji YAMAMOTO
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Patent number: 11069771Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type having a first main surface at one side and a second main surface at another side, a trench gate structure including a gate trench formed in the first main surface of the semiconductor layer, and a gate electrode embedded in the gate trench via a gate insulating layer, a trench source structure including a source trench formed deeper than the gate trench and across an interval from the gate trench in the first main surface of the semiconductor layer, a source electrode embedded in the source trench, and a deep well region of a second conductivity type formed in a region of the semiconductor layer along the source trench, a ratio of a depth of the trench source structure with respect to a depth of the trench gate structure being not less than 1.5 and not more than 4.Type: GrantFiled: May 17, 2018Date of Patent: July 20, 2021Assignee: ROHM CO., LTD.Inventors: Minoru Nakagawa, Yuki Nakano, Masatoshi Aketa, Masaya Ueno, Seigo Mori, Kenji Yamamoto
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Patent number: 10804388Abstract: A semiconductor device 1 includes a trench gate structure 6 formed in a surface layer portion of a first principal surface of a semiconductor layer. A source region 10 and a well region 11 are formed in a surface layer portion of the first principal surface of the semiconductor layer at a side of the trench gate structure 6. The well region 11 is formed in a region at a side of the second principal surface of the semiconductor layer with respect to the source region 10. A channel is formed along the trench gate structure 6 in a portion of the well region 11. A multilayer region 22 is formed in a region between the trench gate structure 6 and the source region 10 in the semiconductor layer. The multilayer region 22 has a p type impurity region 20 formed in the surface layer portion of the first principal surface of the semiconductor layer and an n type impurity region 21 formed in a side of the second principal surface of the semiconductor layer with respect to the second conductivity type impurity region 20.Type: GrantFiled: January 16, 2017Date of Patent: October 13, 2020Assignee: ROHM CO., LTD.Inventors: Minoru Nakagawa, Seigo Mori, Takui Sakaguchi, Masatoshi Aketa, Yuki Nakano
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Publication number: 20200243641Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type having a first main surface at one side and a second main surface at another side, a trench gate structure including a gate trench formed in the first main surface of the semiconductor layer, and a gate electrode embedded in the gate trench via a gate insulating layer, a trench source structure including a source trench formed deeper than the gate trench and across an interval from the gate trench in the first main surface of the semiconductor layer, a source electrode embedded in the source trench, and a deep well region of a second conductivity type formed in a region of the semiconductor layer along the source trench, a ratio of a depth of the trench source structure with respect to a depth of the trench gate structure being not less than 1.5 and not more than 4.Type: ApplicationFiled: May 17, 2018Publication date: July 30, 2020Inventors: Minoru NAKAGAWA, Yuki NAKANO, Masatoshi AKETA, Masaya UENO, Seigo MORI, Kenji YAMAMOTO
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Publication number: 20200098910Abstract: A semiconductor device 1 includes a trench gate structure 6 formed in a surface layer portion of a first principal surface of a semiconductor layer. A source region 10 and a well region 11 are formed in a surface layer portion of the first principal surface of the semiconductor layer at a side of the trench gate structure 6. The well region 11 is formed in a region at a side of the second principal surface of the semiconductor layer with respect to the source region 10. A channel is formed along the trench gate structure 6 in a portion of the well region 11. A multilayer region 22 is formed in a region between the trench gate structure 6 and the source region 10 in the semiconductor layer. The multilayer region 22 has a p type impurity region 20 formed in the surface layer portion of the first principal surface of the semiconductor layer and an n type impurity region 21 formed in a side of the second principal surface of the semiconductor layer with respect to the second conductivity type impurity region 20.Type: ApplicationFiled: January 16, 2017Publication date: March 26, 2020Inventors: Minoru NAKAGAWA, Seigo MORI, Takui SAKAGUCHI, Masatoshi AKETA, Yuki NAKANO
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Publication number: 20170002900Abstract: In at least one embodiment, a continuously variable transmission includes a push arm with a power roller and a drive roller, a support frame at an input side for supporting a supporting point of the push arm, a cam arm with a cam mount at upper side and lower side thereof, an outer circumferential support frame for supporting the cam arm, a drive arm with a pawl, a ring gear having a ratchet mechanism of meshing with the pawl, wherein the cam arm is capable of being stored or being pushed out, and a continuously variable speed drive is carried out by from the output on one-on-one level of the input made by support frame at an input side to the continuously output.Type: ApplicationFiled: October 24, 2014Publication date: January 5, 2017Inventor: Minoru Nakagawa
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Publication number: 20150308544Abstract: Continuously variable transmission mechanism wherein a push arm provided with a power roller (9) and a drive roller (8) being supported by a support frame (4) which supports a planet gear (11) that mesh with a sun gear (12), a ring type of an outer circumferential support frame (5) supporting a cam arm (7a,b,c) with a cam mount on the above and below thereof, an outer cam (3), a control gear (6) being provided around an outer circumference of a drive arm (7a,b,c) with a claw supported by a central shaft, a ring gear (10) which a ratchet is minced, and a planetary gear constitution, instead of a planet gear control driving using a planetary gear structure, and, wherein the cam arm (2) is pushed by the control gear (6) to attain a reciprocating drive the push arm (1) and further the drive arm (7), via an one-way mechanism a drive to an opposite direction for the input is rendered to a ring gear (10) rotating in the same direction for the input to add a power of a rotation drive to an opposite direction for tType: ApplicationFiled: July 22, 2013Publication date: October 29, 2015Inventor: Minoru NAKAGAWA
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Publication number: 20150167795Abstract: It is possible to allow the output which is inputted from a “Planetary gear self-actuating control continuous variable mechanism” of the prior application, JP2012-138212, to always ensure one-to-one input to the output to attain a high continuously variable output by coupling drives with the documented configuration.Type: ApplicationFiled: February 26, 2015Publication date: June 18, 2015Inventor: Minoru NAKAGAWA
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Publication number: 20150126317Abstract: Provided is a planetary gear-type continuously variable transmission mechanism which is capable of smooth continuous variation. A support frame (4), which supports parent/child planet gears (7) provided with a one-way mechanism (10), and push gears (1) that mesh with the small gears of the parent/child planet gears (7) and are provided with power rollers, is provided inside a member in which a ring shaped outer periphery support frame (5) that supports cam arms (2) having cam peaks at the top and bottom thereof, and an outer cam (3) that has cams that push out the cam arms, are meshed by a control gear (6), and a sun gear meshes with the large gears of the parent/child planet gears. The support frame (4) is rotated, pushing the power rollers of the push gears (1) against the inner wall surface of the outer periphery support frame (5), stopping the rotation of the parent/child planet gears (7), thus creating rotational drive and obtaining drive from the sun gear.Type: ApplicationFiled: June 3, 2013Publication date: May 7, 2015Inventor: Minoru Nakagawa
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Patent number: 7176014Abstract: A solid medium having a 10 minute-average water absorption rate of at least 0.05 ml/minute, which is obtainable by a method for producing a solid medium comprising the steps of dissolving components of the solid medium other than solvent water into the solvent water, solidifying the obtained solution, and drying the solidified medium to remove water, wherein water is removed in such an amount that the solid medium after the removal of water should have the 10 minute-average water absorption rate of at least 0.05 ml/minute, and the amount of the solvent water is larger than a prescribed amount by an amount almost equal to the amount of the water to be removed. The solid medium does not cause growth inhibition of microorganisms due to drying, shows a superior water absorption rate to enable application of a larger amount of a sample in a short period of time, and is suitable for quick and accurate measurement tests of microbial numbers.Type: GrantFiled: August 9, 2001Date of Patent: February 13, 2007Assignee: Morinaga Milk Industry Co., Ltd.Inventors: Kazuyoshi Sotoyama, Yasuo Fukuwatari, Yoichiro Yano, Kenji Kiyotaki, Minoru Nakagawa, Kenichiro Karino, Kazue Sasaki
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Publication number: 20040041123Abstract: A solid medium having a 10 minute-average water absorption rate of at least 0.05 ml/minute, which is obtainable by a method for producing a solid medium comprising the steps of dissolving components of the solid medium other than solvent water into the solvent water, solidifying the obtained solution, and drying the solidified medium to remove water, wherein water is removed in such an amount that the solid medium after the removal of water should have the 10 minute-average water absorption rate of at least 0.05 ml/minute, and the amount of the solvent water is larger than a prescribed amount by an amount almost equal to the amount of the water to be removed. The solid medium does not cause growth inhibition of microorganisms due to drying, shows a superior water absorption rate to enable application of a larger amount of a sample in a short period of time, and is suitable for quick and accurate measurement tests of microbial numbers.Type: ApplicationFiled: May 20, 2003Publication date: March 4, 2004Inventors: Kazuyoshi Sotoyama, Yasuo Fukuwatari, Yoichiro Yano, Kenji Kiyotaki, Minoru Nakagawa, Kenichiro Karin, Kazue Sasaki