Abstract: An object is to provide a control device, a control method thereof, and a control program that can simplify the configuration. The control device (C1) configured to control a control target instrument includes: an input unit (IN1) configured to accept input of an input signal including input information and transmit the input information to a communication network (NW); and a CPU_1 configured to receive the input information from the input unit (IN1) via the communication network (NW) and perform control based on the input information, and the CPU_1 transmits the received input information via the communication network (NW) to a CPU_2 configured to control a control target instrument in another device (C2) provided independently of the control device (C1).

Abstract: The control device is configured to communicate with another device via a communication network, and comprises: a key acquisition unit configured to acquire, from a key distribution server via the communication network, an encryption key with a life period for performing encrypted communication with the another device; an encrypted communication processing unit configured to perform the encrypted communication with the another device using the encryption key within the life period; a server state detection unit configured to detect a key acquisition disabled state where acquisition of the encryption key by the key acquisition unit is disabled; and a life extension unit configured to perform extension processing for extending the life period if the key acquisition disabled state is detected.

Abstract: A computing device for configuring a redundant system includes: a detection unit configured to detect another computing device newly added to the redundant system during operation of the computing device; and a construction processing unit configured to execute construction processing for constructing a redundant configuration with the other computing device.

Abstract: An information processing apparatus includes an MMU that translates between a virtual address and a physical address on the basis of a translation table for translation between physical addresses that are addresses in physical memory and virtual addresses that are addresses in virtual memory. Stored in a RAM are page table information indicating a page table, as well as error detection information attached to the page table information for detecting the presence or absence of an error in translation between a virtual address and a physical address performed by the MMU. A CPU detects the presence or absence of an error in translation between a virtual address and a physical address performed by the MMU on the basis of the error detection information.

Abstract: A CPU changes the operating mode to a test mode in which the CPU does not terminate a program being executed even if an MMU outputs a CPU exception notification, outputs an address signal for causing the MMU to output a CPU exception notification to the MMU in the test mode, and detects whether or not a CPU exception notification is input after the address signal is output to the MMU. This allows inspection as to whether or not a fault that prevents detection of an illegal access has occurred in the MMU while executing another program.

Abstract: An information processing apparatus includes an MMU that translates between a virtual address and a physical address on the basis of a translation table for translation between physical addresses that are addresses in physical memory and virtual addresses that are addresses in virtual memory. Stored in a RAM are page table information indicating a page table, as well as error detection information attached to the page table information for detecting the presence or absence of an error in translation between a virtual address and a physical address performed by the MMU. A CPU detects the presence or absence of an error in translation between a virtual address and a physical address performed by the MMU on the basis of the error detection information.

Abstract: A CPU changes the operating mode to a test mode in which the CPU does not terminate a program being executed even if an MMU outputs a CPU exception notification, outputs an address signal for causing the MMU to output a CPU exception notification to the MMU in the test mode, and detects whether or not a CPU exception notification is input after the address signal is output to the MMU. This allows inspection as to whether or not a fault that prevents detection of an illegal access has occurred in the MMU while executing another program.