Abstract: A semiconductor integrated circuit including a logic circuit is disclosed, in which the decoder area can be reduced and which has an effect of reduction of the whole chip size. Among the MOS FETs included in the logic circuit, those other than a MOS FET for supplying electric charges via an output terminal have threshold voltage values lower than the threshold voltage value of the MOS FET for supplying electric charges. The direction of the gate width of each MOS FET is perpendicular to the direction along which word lines extend in the memory cell areas, and all of the MOS FETs are aligned in a direction perpendicular to the direction along which the word lines extend.

Abstract: A semiconductor integrated circuit including a logic circuit is disclosed, in which the decoder area can be reduced and which has an effect of reduction of the whole chip size. Among the MOS FETs included in the logic circuit, those other than a MOS FET for supplying electric charges via an output terminal have threshold voltage values lower than the threshold voltage value of the MOS FET for supplying electric charges. The direction of the gate width of each MOS FET is perpendicular to the direction along which word lines extend in the memory cell areas, and all of the MOS FETs are aligned in a direction perpendicular to the direction along which the word lines extend.

Abstract: A semiconductor integrated circuit including a logic circuit is disclosed, in which the decoder area can be reduced and which has an effect of reduction of the whole chip size. Among the MOS FETs included in the logic circuit, those other than a MOS FET for supplying electric charges via an output terminal have threshold voltage values lower than the threshold voltage value of the MOS FET for supplying electric charges. The direction of the gate width of each MOS FET is perpendicular to the direction along which word lines extend in the memory cell areas, and all of the MOS FETs are aligned in a direction perpendicular to the direction along which the word lines extend.

Abstract: A semiconductor integrated circuit including a logic circuit is disclosed, in which the decoder area can be reduced and which has an effect of reduction of the whole chip size. Among the MOS FETs included in the logic circuit, those other than a MOS FET for supplying electric charges via an output terminal have threshold voltage values lower than the threshold voltage value of the MOS FET for supplying electric charges. The direction of the gate width of each MOS FET is perpendicular to the direction along which word lines extend in the memory cell areas, and all of the MOS FETs are aligned in a direction perpendicular to the direction along which the word lines extend.

Abstract: A semiconductor integrated circuit including a logic circuit is disclosed, in which the decoder area can be reduced and which has an effect of reduction of the whole chip size. Among the MOS FETs included in the logic circuit, those other than a MOS FET for supplying electric charges via an output terminal have threshold voltage values lower than the threshold voltage value of the MOS FET for supplying electric charges. The direction of the gate width of each MOS FET is perpendicular to the direction along which word lines extend in the memory cell areas, and all of the MOS FETs are aligned in a direction perpendicular to the direction along which the word lines extend.

Abstract: A semiconductor integrated circuit including a logic circuit is disclosed, in which the decoder area can be reduced and which has an effect of reduction of the whole chip size. Among the MOS FETs included in the logic circuit, those other than a MOS FET for supplying electric charges via an output terminal have threshold voltage values lower than the threshold voltage value of the MOS FET for supplying electric charges. The direction of the gate width of each MOS FET is perpendicular to the direction along which word lines extend in the memory cell areas, and all of the MOS FETs are aligned in a direction perpendicular to the direction along which the word lines extend.

Abstract: A non-volatile memory device has a built-in test pattern generator used during diagnostics of control signal lines. An internal test pattern generator supplies a test pattern to digit lines so that short circuit between decoded signal lines to a column selector changes the internal test pattern, thereby effectively screening out a defective product. Digit lines of the memory device are sequentially coupled through the column selector with a sense amplifier circuit in a diagnostic operation to see whether or not any defective component is incorporated therein.

Abstract: An erasable and programmable ROM with an identification code includes an internal circuit operating as an EPROM, a code reading circuit having a code setting circuit for storing a predetermined identification code, an output circuit, and a switching circuit for transferring an output of an internal circuit to the output circuit. The switching circuit is turned on to transfer the output signal of the internal circuit to the output circuit directly, when information in the internal circuit is read out. On the other hand, the switching circuit is turned off to separate the output circuit from the internal circuit, when the identification code is read out from the code setting circuit.

Abstract: A write-in voltage source is incorporated in an electrically erasable read only memory device for supplying a write-in voltage level to memory circuits of a redundant unit as well as a data storage, and comprises a first control circuit responsive to a first instruction signal indicative of a power voltage level or a write-in voltage level and producing first and second control signals complementary to each other, a second control circuit responsive to a second instruction signal indicative of a ground voltage level and producing third and fourth control signals complementary to each other, a first level-shifting circuit responsive to the first to third control signals and producing one of the write-in voltage level, the power voltage level and the ground voltage level, and a second level-shifting circuit responsive to the first, second, and fourth control signals and producing one of the write-in voltage level, the power voltage level and the ground voltage level so that the first and second level-shifting c