Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate having a first surface. The semiconductor substrate has therein a first region. The first region is at the first surface and contains a dopant of a first conductivity type. A first contact contacts the first region at the first surface. The first contact has a first metal layer that contacts the first region, a second metal layer covering the first metal layer, and a third metal layer covering the second metal layer.

Abstract: According to one embodiment, a memory system includes a first memory and a controller. The controller includes first and second decoders, first and second circuits, a register, and a switching circuit. The first and second decoders decode first and second commands respectively, which include first and second addresses respectively. The first and second circuits access the first memory using the first and second addresses respectively. A value stored in the register is changeable by a host. The switching circuit switches between the first and second circuits to access the first memory according to the value in the register.

Abstract: A semiconductor storage device includes a first substrate, a second substrate, a first stacked body, and a second stacked body. The first stacked body is provided between the first substrate and the second substrate and includes a first trace, a first pad connected to the first trace, and a first insulator. The second stacked body is provided between the first stacked body and the second substrate and includes a second trace, a second pad connected to the second trace, and a second insulator. The first pad includes a plurality of first electrode portions connected to the first trace. The first insulator is provided between the plurality of first electrode portions. The plurality of first electrode portions are bonded to the second pad.

Abstract: According to one embodiment, a memory system includes a first memory and a controller. The controller includes first and second decoders, first and second circuits, a register, and a switching circuit. The first and second decoders decode first and second commands respectively, which include first and second addresses respectively. The first and second circuits access the first memory using the first and second addresses respectively. A value stored in the register is changeable by a host. The switching circuit switches between the first and second circuits to access the first memory according to the value in the register.

Abstract: A semiconductor device according to an embodiment includes first and second chips, and a first conductor. The first chip includes a first substrate, a first circuit and a first joint metal. The first circuit is provided on the first substrate. The first joint metal is connected to the first circuit. The second chip includes a second substrate, a second circuit, and a second joint metal. The second substrate includes P-type and N-type well regions. The second circuit is provided on the second substrate and includes a first transistor. The second joint metal is connected to the second circuit and the first joint metal. The first conductor is connected to the N-type well region from a top region of the second chip. The P-type well region is arranged between a gate electrode of the first transistor and the N-type well region.

Abstract: A semiconductor device includes a semiconductor substrate, a source or drain layer provided in the semiconductor substrate, a gate insulation layer provided on a surface of the semiconductor substrate, and a gate electrode that is provided on the gate insulation layer. The semiconductor device further includes a first contact that is provided on the source or drain layer, the first contact including a stacked body in which a plurality of first layers and one or more second layers are alternately stacked, and a second contact that faces at least one of a side surface and an upper surface of the first contact disposed on the source or drain layer.

Abstract: A semiconductor device according to an embodiment includes first and second chips, and a first conductor. The first chip includes a first substrate, a first circuit and a first joint metal. The first circuit is provided on the first substrate. The first joint metal is connected to the first circuit. The second chip includes a second substrate, a second circuit, and a second joint metal. The second substrate includes P-type and N-type well regions. The second circuit is provided on the second substrate and includes a first transistor. The second joint metal is connected to the second circuit and the first joint metal. The first conductor is connected to the N-type well region from a top region of the second chip. The P-type well region is arranged between a gate electrode of the first transistor and the N-type well region.

Abstract: A storage device including a transistor portion including a transistor, a plurality of interlayer insulating films provided above the transistor portion, a plurality of first conductive layers provided respectively between the plurality of interlayer insulating films, and a second conductive layer extending through the plurality of interlayer insulating films and the plurality of first conductive layers, the second conductive layer having one end electrically connected to the transistor portion, and a part that extends beyond a portion of the transistor portion.

Abstract: A semiconductor device includes a semiconductor substrate, a source or drain layer provided in the semiconductor substrate, a gate insulation layer provided on a surface of the semiconductor substrate, and a gate electrode that is provided on the gate insulation layer. The semiconductor device further includes a first contact that is provided on the source or drain layer, the first contact including a stacked body in which a plurality of first layers and one or more second layers are alternately stacked, and a second contact that faces at least one of a side surface and an upper surface of the first contact disposed on the source or drain layer.

Abstract: A storage device including a transistor portion including a transistor, a plurality of interlayer insulating films provided above the transistor portion, a plurality of first conductive layers provided respectively between the plurality of interlayer insulating films, and a second conductive layer extending through the plurality of interlayer insulating films and the plurality of first conductive layers, the second conductive layer having one end electrically connected to the transistor portion, and a part that extends beyond a portion of the transistor portion.

Abstract: A semiconductor device includes a semiconductor pillar and a control electrode. The semiconductor pillar extends in a first direction, and includes a first region, a second region and an intermediate region provided along the first direction. The intermediate region is positioned between the first region and the second region. The control electrode is disposed at a position so that the control electrode faces the intermediate region via an insulating film. The semiconductor pillar is provided so that a minimum width of the intermediate region in a second direction perpendicular to the first direction is narrower than a first width of the first region in the second direction and a second width of the second region in the second direction.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a first electrode. The third semiconductor layer is provided between the first semiconductor layer and the second semiconductor layer. The first electrode opposes the third semiconductor layer. An orientation ratio of the third semiconductor layer is higher than an orientation ratio of the first semiconductor layer.

Abstract: According to one embodiment, a semiconductor device includes first to third semiconductor regions and first to third conductors. The second semiconductor region is separated from the first semiconductor region in a first direction. The third semiconductor region is provided between the first and the second semiconductor regions. The third conductor is separated from the third semiconductor region in a second direction intersecting the first direction. The third semiconductor region includes first and second partial regions. The first partial region includes a first metal element, and is amorphous. The second partial region is stacked with the first partial region in the second direction, and is polycrystalline. A first concentration of the first metal element in the first partial region is higher than a second concentration of the first metal element in the second partial region, or the second partial region does not include the first metal element.

Abstract: In a system in which a plurality of information processing devices that access data stored in one device according to individual clocks are connected, and data regarding access from another device flows through a path relaying the plurality of information processing devices, a data transfer control system that increases data transfer performance between the information processing devices is disclosed.

Abstract: According to one embodiment, a semiconductor device includes first to third semiconductor regions and first to third conductors. The second semiconductor region is separated from the first semiconductor region in a first direction. The third semiconductor region is provided between the first and the second semiconductor regions. The third conductor is separated from the third semiconductor region in a second direction intersecting the first direction. The third semiconductor region includes first and second partial regions. The first partial region includes a first metal element, and is amorphous. The second partial region is stacked with the first partial region in the second direction, and is polycrystalline. A first concentration of the first metal element in the first partial region is higher than a second concentration of the first metal element in the second partial region, or the second partial region does not include the first metal element.

Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a first electrode. The third semiconductor layer is provided between the first semiconductor layer and the second semiconductor layer. The first electrode opposes the third semiconductor layer. An orientation ratio of the third semiconductor layer is higher than an orientation ratio of the first semiconductor layer.

Abstract: Write-leveling, a write-leveling control unit (250) adjusts the delay amounts of DQS control unit (242) and a DQ control unit (244), at first, within a range of less than one clock cycle. Then, with respect to each SDRAM (282), a read-data row acquired by performing a read after a write of an expected value data row is compared value data row, and depending upon the comparison result, the delay amounts of the DQS control unit (242) and the DQ control unit (244) are adjusted in clock-cycle units. At the above write-time, control is performed so that the DQS control unit (242) outputs a data strobe signal (DQS) which is 2×M clock cycles longer than a burst length defined according to a specification, and the DQ control unit (244) adds M units each of data before and after a number of units of expected value data rows that match the burst length in order to output the data.

Abstract: An airbag according to the present invention has: an airbag main body that is provided with a gas introduction opening; and an inner cloth portion that is arranged to cover the gas introduction opening in the airbag main body. The inner cloth portion has a first and a second opening end parts, and is fixed to a peripheral edge part of the gas introduction opening of the airbag main body while a position of the inner cloth portion is superimposed with the gas introduction opening of the airbag main body. In this manner, an airbag is caused to inflate and expand more speedily and widely in a direction which is orthogonal to an occupant's side direction, and an occupant can be buffered and supported in a stable manner so as to have a wide area from a front side irrespective of whatsoever posture seated by the occupant may be.

Abstract: An airbag according to the present invention has: an airbag main body that is provided with a gas introduction opening; and an inner cloth portion that is arranged to cover the gas introduction opening in the airbag main body. The inner cloth portion has a first and a second opening end parts, and is fixed to a peripheral edge part of the gas introduction opening of the airbag main body while a position of the inner cloth portion is superimposed with the gas introduction opening of the airbag main body. In this manner, an airbag is caused to inflate and expand more speedily and widely in a direction which is orthogonal to an occupant's side direction, and an occupant can be buffered and supported in a stable manner so as to have a wide area from a front side irrespective of whatsoever posture seated by the occupant may be.

Abstract: Write-leveling, a write-leveling control unit(250) adjusts the delay amounts of DQS control unit(242) and a DQ control unit(244), at first, within a range of less than one clock cycle. Then, with respect to each SDRAM(282), a read-data row acquired by performing a read after a write of an expected value data row is compared value data row, and depending upon the comparison result, the delay amounts of the DQS control unit(242) and the DQ control unit(244) are adjusted in clock-cycle units. At the above write-time, control is performed so that the DQS control unit(242) outputs a data strobe signal(DQS) which is 2×M clock cycles longer than a burst length defined according to a specification, and the DQ control unit(244) adds M units each of data before and after a number of units of expected value data rows that match the burst length in order to output the data.