Patents by Inventor Minoru Ooishi

Minoru Ooishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5115410
    Abstract: A program processing system including a program input device for entering optional programs for performing an optional function, an optional-program memory for storing the optional programs, a standard-program memory which stores a standard program for performing a basic function; a commanding device for designating one of the optional programs, for execution of the designated optional program, and a controller for retrieving the designated optional program from the optional-program memory, to perform the corresponding optional function, if the designated optional program is stored in the optional-program memory, the control means retrieving the standard program from the standard-program memory, to perform the basic function, if the designated optional program is not stored in the optional-program memory means.
    Type: Grant
    Filed: August 4, 1988
    Date of Patent: May 19, 1992
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventors: Keiichi Hirata, Yoshinari Morimoto, Minoru Ooishi, Tomohiro Ban, Akihiro Furukawa
  • Patent number: 4963042
    Abstract: In a text processing device, provided is an improved tabulation function. The vertical positions of horizontal ruled lines dividing two rows are calculated based upon the intervals existing between these columns. If the row interval is expanded or changed, the horizontal ruled lines remain consistent in a predetermined relationship with a character string.
    Type: Grant
    Filed: March 27, 1989
    Date of Patent: October 16, 1990
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventors: Yasushi Kawakami, Keiichi Hirata, Mizuho Kamisaka, Miyako Mukai, Tomohiro Ban, Minoru Ooishi
  • Patent number: 4379997
    Abstract: A power amplifier which has a muting circuit bringing the power amplifier into a muting condition when an excessively large input signal is applied. The power amplifier comprises a preamplifying stage and a power amplifying stage. The preamplifying stage includes at least one transistor for driving the power amplifying stage. The collector of the transistor is coupled to one power source terminal. The emitter of the transistor is coupled to the other power source terminal through an electronic switch, and to the first power source terminal through a resistor. The electronic switch selectively connects the emitter of the transistor to one of the power source terminals.
    Type: Grant
    Filed: January 5, 1981
    Date of Patent: April 12, 1983
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Minoru Ooishi, Teruji Mochizuki, Yutaka Suzuki