Patents by Inventor Minoru Saeki

Minoru Saeki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10223110
    Abstract: There is a need to provide a central processing unit capable of improving the resistance to power analysis attack without changing programs, lowering clock frequencies, and greatly redesigning a central processing unit of the related art. In a central processing unit, an arithmetic unit is capable of performing arithmetic operation using data irrelevant to data stored in a register group. A control unit allows the arithmetic unit to perform arithmetic processing corresponding to an incorporated instruction. At this time, the control unit allows the arithmetic unit to perform arithmetic processing using the irrelevant data during a first one-clock cycle.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: March 5, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Minoru Saeki
  • Publication number: 20180069874
    Abstract: The present invention relates to an attack detection apparatus that detects an attack against a communication network between devices, and improves information security of the communication network. The attack detection apparatus has a CAN (Controller Area Network) that transfers a signal to a plurality of nodes by a differential voltage between two signal lines, and a short circuit detector that monitors the signal transferred by the two signal lines of the CAN, and detects a short circuit between the two signal lines on the basis of a change in the signal indicating a characteristic of a short circuit attack by an unauthorized node.
    Type: Application
    Filed: May 15, 2015
    Publication date: March 8, 2018
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Minoru SAEKI, Takeshi SUGAWARA
  • Publication number: 20150338878
    Abstract: There is a need for providing a battery-less integrated circuit (IC) card capable of operating in accordance with a contact usage or a non-contact usage, preventing coprocessor throughput from degrading despite a decreased clock frequency for reduced power consumption under non-contact usage, and ensuring high-speed processing under non-contact usage. A dual interface card is a battery-less IC card capable of operating in accordance with a contact usage or a non-contact usage. The dual interface card operates at a high clock under contact usage and at a low clock under non-contact usage. A targeted operation comprises a plurality of different basic operations. The dual interface card comprises a basic arithmetic circuit group. Under the contact usage, the basic arithmetic circuit group performs one basic operation of the targeted operation at one cycle. Under the non-contact usage, the basic arithmetic circuit group sequentially performs at least two basic operations of the targeted operation at one cycle.
    Type: Application
    Filed: August 5, 2015
    Publication date: November 26, 2015
    Inventors: Daisuke SUZUKI, Minoru SAEKI, Yuichiro NARIYOSHI
  • Patent number: 9116693
    Abstract: There is a need for providing a battery-less integrated circuit (IC) card capable of operating in accordance with a contact usage or a non-contact usage, preventing coprocessor throughput from degrading despite a decreased clock frequency for reduced power consumption under non-contact usage, and ensuring high-speed processing under non-contact usage. A dual interface card is a battery-less IC card capable of operating in accordance with a contact usage or a non-contact usage. The dual interface card operates at a high clock under contact usage and at a low clock under non-contact usage. A targeted operation comprises a plurality of different basic operations. The dual interface card comprises a basic arithmetic circuit group. Under the contact usage, the basic arithmetic circuit group performs one basic operation of the targeted operation at one cycle. Under the non-contact usage, the basic arithmetic circuit group sequentially performs at least two basic operations of the targeted operation at one cycle.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: August 25, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Daisuke Suzuki, Minoru Saeki, Yuichiro Nariyoshi
  • Publication number: 20140068231
    Abstract: There is a need to provide a central processing unit capable of improving the resistance to power analysis attack without changing programs, lowering clock frequencies, and greatly redesigning a central processing unit of the related art. In a central processing unit, an arithmetic unit is capable of performing arithmetic operation using data irrelevant to data stored in a register group. A control unit allows the arithmetic unit to perform arithmetic processing corresponding to an incorporated instruction. At this time, the control unit allows the arithmetic unit to perform arithmetic processing using the irrelevant data during a first one-clock cycle.
    Type: Application
    Filed: August 29, 2013
    Publication date: March 6, 2014
    Applicant: Renesas Electronics Corporation
    Inventor: Minoru SAEKI
  • Patent number: 8577942
    Abstract: An electronic device that defends against an attack trying to identify confidential information from power consumption is provided without any circuit that performs a complementary operation to eliminate bias in power consumption. An elementary device A 100 is formed by a plurality of transistors 101-112. The elementary device A 100 receives inputs signals x1, x2, a random number r, and a control signal en, and outputs z. The output z is obtained by XORing (x1^r)&(x2^r) with the random number r. After the state transitions of the input signal, x1, x2, and the random number r, are settled, the control signal en is used to output z. This makes the signal transition rate of the output z equal, thereby defending against an attack trying to identify confidential information from power consumption.
    Type: Grant
    Filed: July 7, 2004
    Date of Patent: November 5, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventors: Daisuke Suzuki, Minoru Saeki
  • Patent number: 8417430
    Abstract: A following distance control device includes a vehicle speed detecting device that detects the vehicle speed VSPD of an own vehicle and outputs a vehicle speed equal to or less than a predetermined speed as zero, a following distance detecting device that detects a following distance between a preceding vehicle and the own vehicle, a first requested acceleration computing device that computes a requested acceleration GBASE from the vehicle speed and the following distance, and a stop determining device that determines the stop of the own vehicle, on the basis of a requested acceleration Greq_pre_0 kph at a time point when the output value of the vehicle speed detecting device becomes zero.
    Type: Grant
    Filed: June 3, 2008
    Date of Patent: April 9, 2013
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Minoru Saeki
  • Publication number: 20120198211
    Abstract: There is a need for providing a battery-less integrated circuit (IC) card capable of operating in accordance with a contact usage or a non-contact usage, preventing coprocessor throughput from degrading despite a decreased clock frequency for reduced power consumption under non-contact usage, and ensuring high-speed processing under non-contact usage. A dual interface card is a battery-less IC card capable of operating in accordance with a contact usage or a non-contact usage. The dual interface card operates at a high clock under contact usage and at a low clock under non-contact usage. A targeted operation comprises a plurality of different basic operations. The dual interface card comprises a basic arithmetic circuit group. Under the contact usage, the basic arithmetic circuit group performs one basic operation of the targeted operation at one cycle. Under the non-contact usage, the basic arithmetic circuit group sequentially performs at least two basic operations of the targeted operation at one cycle.
    Type: Application
    Filed: April 10, 2012
    Publication date: August 2, 2012
    Applicant: Renesas Electronics Corporation
    Inventors: Daisuke SUZUKI, Minoru Saeki, Yuichiro Nariyoshi
  • Patent number: 8219847
    Abstract: There is a need for providing a battery-less integrated circuit (IC) card capable of operating in accordance with a contact usage or a non-contact usage, preventing coprocessor throughput from degrading despite a decreased clock frequency for reduced power consumption under non-contact usage, and ensuring high-speed processing under non-contact usage. A dual interface card is a battery-less IC card capable of operating in accordance with a contact usage or a non-contact usage. The dual interface card operates at a high clock under contact usage and at a low clock under non-contact usage. A targeted operation comprises a plurality of different basic operations. The dual interface card comprises a basic arithmetic circuit group. Under the contact usage, the basic arithmetic circuit group performs one basic operation of the targeted operation at one cycle. Under the non-contact usage, the basic arithmetic circuit group sequentially performs at least two basic operations of the targeted operation at one cycle.
    Type: Grant
    Filed: October 23, 2009
    Date of Patent: July 10, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Daisuke Suzuki, Minoru Saeki, Yuichiro Nariyoshi
  • Patent number: 8195360
    Abstract: A curve radius estimating device (100) configured to estimate a curve radius of a lane on which a self vehicle is driving includes a first curve radius calculating part (110) configured to calculate a first curve radius on a steering angle, a second curve radius calculating part (111) configured to calculate a second curve radius on a yaw rate, and a curve radius estimating part (112) configured to estimate a curve radius by combining the first curve radius and the second curve radius at a predetermined combination ratio. The curve radius estimating part (112) changes the predetermined combination ratio depending on a vehicle speed.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: June 5, 2012
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Minoru Nakadori, Minoru Saeki
  • Publication number: 20110270466
    Abstract: A curve radius estimating device (100) configured to estimate a curve radius of a lane on which a self vehicle is driving includes a first curve radius calculating part (110) configured to calculate a first curve radius on a steering angle, a second curve radius calculating part (111) configured to calculate a second curve radius on a yaw rate, and a curve radius estimating part (112) configured to estimate a curve radius by combining the first curve radius and the second curve radius at a predetermined combination ratio. The curve radius estimating part (112) changes the predetermined combination ratio depending on a vehicle speed.
    Type: Application
    Filed: July 11, 2011
    Publication date: November 3, 2011
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Minoru NAKADORI, Minoru Saeki
  • Publication number: 20110022852
    Abstract: A flowchart shows a general processing procedure of cryptographic computation executed by a cryptographic computation apparatus 100. A power supply is turned on in S101. In S102, a cryptographic computation execution program is fetched, and initialization such as memory allocation is performed. In S103, a plaintext is input, and the plaintext is stored by a RAM or the like. In S104, the cryptographic computation execution program is fetched, and the cryptographic computation is performed using a resistor or the RAM. In S105, a ciphertext is extracted. In S106, a CPU determines whether or not to continue a cryptographic computation process. In case of continuation, the flow returns to S102. In the above encryption process of S102 through S106, a resistor/memory input process (S200) is interposed between S103 and S104. In S200, before the cryptographic computation (S104) is started, data (e.g.
    Type: Application
    Filed: March 25, 2008
    Publication date: January 27, 2011
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Tsuneo Sato, Minoru Saeki, Manabu Misawa
  • Publication number: 20100204870
    Abstract: A following distance control device includes a vehicle speed detecting device that detects the vehicle speed VSPD of an own vehicle and outputs a vehicle speed equal to or less than a predetermined speed as zero, a following distance detecting device that detects a following distance between a preceding vehicle and the own vehicle, a first requested acceleration computing device that computes a requested acceleration GBASE from the vehicle speed and the following distance, and a stop determining device that determines the stop of the own vehicle, on the basis of a requested acceleration Greg_pre_0 kph at a time point when the output value of the vehicle speed detecting device becomes zero.
    Type: Application
    Filed: June 3, 2008
    Publication date: August 12, 2010
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Minoru Saeki
  • Publication number: 20100122108
    Abstract: There is a need for providing a battery-less integrated circuit (IC) card capable of operating in accordance with a contact usage or a non-contact usage, preventing coprocessor throughput from degrading despite a decreased clock frequency for reduced power consumption under non-contact usage, and ensuring high-speed processing under non-contact usage. A dual interface card is a battery-less IC card capable of operating in accordance with a contact usage or a non-contact usage. The dual interface card operates at a high clock under contact usage and at a low clock under non-contact usage. A targeted operation comprises a plurality of different basic operations. The dual interface card comprises a basic arithmetic circuit group. Under the contact usage, the basic arithmetic circuit group performs one basic operation of the targeted operation at one cycle. Under the non-contact usage, the basic arithmetic circuit group sequentially performs at least two basic operations of the targeted operation at one cycle.
    Type: Application
    Filed: October 23, 2009
    Publication date: May 13, 2010
    Inventors: Daisuke Suzuki, Minoru Saeki, Yuichiro Nariyoshi
  • Patent number: 7668638
    Abstract: A disclosed inter-vehicle distance control apparatus for controlling an inter-vehicle distance between a present vehicle equipped with this apparatus and a preceding vehicle traveling ahead of the present vehicle changes a target deceleration of the present vehicle and/or a deceleration gradient of the present vehicle, with which the deceleration reaches the target deceleration of the present vehicle, between when the present vehicle is under a first deceleration condition in which the present vehicle decelerates under the circumstance where the inter-vehicle distance between the present vehicle and the preceding vehicle is relatively short and when the present vehicle is under a second deceleration condition in which the present vehicle decelerates under the circumstance where the inter-vehicle distance is relatively long.
    Type: Grant
    Filed: July 25, 2005
    Date of Patent: February 23, 2010
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Minoru Saeki
  • Patent number: 7460965
    Abstract: It is a purpose to evaluate a tamper resistance of an actual circuit with a high accuracy and at a high speed in an upstream process of a circuit design.
    Type: Grant
    Filed: July 7, 2004
    Date of Patent: December 2, 2008
    Assignee: Mitsubishi Electric Corporation
    Inventors: Minoru Saeki, Daisuke Suzuki
  • Patent number: 7447577
    Abstract: A curve's radius of a road on which a vehicle shall run is estimated based on actual speed, yaw rate, and steering angle of the vehicle. Accordingly, during a transition state of the vehicle, the curve's radius can be estimated with the actual yaw rate taking into account the actual steering angle that can reflect more accurately turning behavior of the vehicle than the actual yaw rate. Therefore, errors in the estimation of the curve's radius due to response delay of the actual yaw rate can be easily reduced even though the yaw rate is used for such estimation.
    Type: Grant
    Filed: December 12, 2003
    Date of Patent: November 4, 2008
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Akira Hattori, Minoru Saeki
  • Publication number: 20080021940
    Abstract: An electronic device that defends against an attack trying to identify confidential information from power consumption is provided without any circuit that performs a complementary operation to eliminate bias in power consumption. An elementary device A 100 is formed by a plurality of transistors 101-112. The elementary device A 100 receives inputs signals x1, x2, a random number r, and a control signal en, and outputs z. The output z is obtained by XORing (x1ˆr)&(x2ˆr) with the random number r. After the state transitions of the input signal, x1, x2, and the random number r, are settled, the control signal en is used to output z. This makes the signal transition rate of the output z equal, thereby defending against an attack trying to identify confidential information from power consumption.
    Type: Application
    Filed: July 7, 2004
    Publication date: January 24, 2008
    Inventors: Daisuke Suzuki, Minoru Saeki
  • Publication number: 20070219735
    Abstract: It is a purpose to evaluate a tamper resistance of an actual circuit with a high accuracy and at a high speed in an upstream process of a circuit design.
    Type: Application
    Filed: July 7, 2004
    Publication date: September 20, 2007
    Inventors: Minoru Saeki, Daisuke Suzuki
  • Publication number: 20060025918
    Abstract: A disclosed inter-vehicle distance control apparatus for controlling an inter-vehicle distance between a present vehicle equipped with this apparatus and a preceding vehicle traveling ahead of the present vehicle changes a target deceleration of the present vehicle and/or a deceleration gradient of the present vehicle, with which the deceleration reaches the target deceleration of the present vehicle, between when the present vehicle is under a first deceleration condition in which the present vehicle decelerates under the circumstance where the inter-vehicle distance between the present vehicle and the preceding vehicle is relatively short and when the present vehicle is under a second deceleration condition in which the present vehicle decelerates under the circumstance where the inter-vehicle distance is relatively long.
    Type: Application
    Filed: July 25, 2005
    Publication date: February 2, 2006
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Minoru Saeki