Patents by Inventor Minoru Sanada

Minoru Sanada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7940064
    Abstract: A temperature regulation plate 106 is divided into at least two areas, a heater 408 for applying a temperature load in correspondence with such areas and its control system are divided and controlled independently to set temperatures, and a cooling source is controlled by comparing the measurements from temperature sensors 409 arranged in respective areas for controlling the heater 408 and switching the measurement for calculating the control output sequentially thus reducing variation in in-plane temperature of a wafer due to heating when an electric load is applied. Since consumption and burning of a probe are prevented, highly reliable wafer level burn-in method and apparatus can be provided.
    Type: Grant
    Filed: May 29, 2006
    Date of Patent: May 10, 2011
    Assignee: Panasonic Corporation
    Inventors: Terutsugu Segawa, Minoru Sanada
  • Patent number: 7768285
    Abstract: Provided is a probe card for semiconductor IC test on one principal surface of which are formed a plurality of probe electrodes, such as bump electrodes (5), and which has, in a peripheral portion thereof, a thin film sheet (9) fixed to a support, such as a ceramics ring (7). A local tension-changed portion (12) is formed in the thin film sheet (9) fixed to the ceramics ring (7) so that a tensile strain is generated, and the plurality of bump electrodes (5) are arranged in prescribed positions that connect electrically to electrodes of each semiconductor IC element of the semiconductor wafer. The tensile strain of the thin film sheet (9) is changed positively and in a sustained manner, whereby the bump electrodes (5) are rearranged in desired positions.
    Type: Grant
    Filed: June 19, 2007
    Date of Patent: August 3, 2010
    Assignee: Panasonic Corporation
    Inventors: Minoru Sanada, Yoshirou Nakata
  • Publication number: 20090160472
    Abstract: Temperature control in wafer-level burn-in is performed such that a set temperature used for the temperature control is corrected using a correction value calculated from the generated heat density of a wafer (101). Thus it is possible to eliminate a difference between the temperature of the wafer heated when an electrical load is applied and a control temperature for applying a thermal load, not depending on the distribution of good devices formed on the wafer (101) and the power consumption of the devices. As a result, the wear and burn of a probe can be prevented and highly reliable screening can be achieved.
    Type: Application
    Filed: June 26, 2006
    Publication date: June 25, 2009
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD
    Inventors: Terutsugu Segawa, Minoru Sanada
  • Publication number: 20090102499
    Abstract: A temperature regulation plate 106 is divided into at least two areas, a heater 408 for applying a temperature load in correspondence with such areas and its control system are divided and controlled independently to set temperatures, and a cooling source is controlled by comparing the measurements from temperature sensors 409 arranged in respective areas for controlling the heater 408 and switching the measurement for calculating the control output sequentially thus reducing variation in in-plane temperature of a wafer due to heating when an electric load is applied. Since consumption and burning of a probe are prevented, highly reliable wafer level burn-in method and apparatus can be provided.
    Type: Application
    Filed: May 29, 2006
    Publication date: April 23, 2009
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Terutsugu Segawa, Minoru Sanada
  • Publication number: 20080150563
    Abstract: Provided is a probe card for semiconductor IC test on one principal surface of which are formed a plurality of probe electrodes, such as bump electrodes (5), and which has, in a peripheral portion thereof, a thin film sheet (9) fixed to a support, such as a ceramics ring (7). A local tension-changed portion (12) is formed in the thin film sheet (9) fixed to the ceramics ring (7) so that a tensile strain is generated, and the plurality of bump electrodes (5) are arranged in prescribed positions that connect electrically to electrodes of each semiconductor IC element of the semiconductor wafer. The tensile strain of the thin film sheet (9) is changed positively and in a sustained manner, whereby the bump electrodes (5) are rearranged in desired positions.
    Type: Application
    Filed: June 19, 2007
    Publication date: June 26, 2008
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Minoru Sanada, Yoshirou Nakata
  • Publication number: 20070009240
    Abstract: A semiconductor test device comprises a substrate having a opposed-wafer surface on which a semiconductor wafer with a plurality of the embedded semiconductor devices is placing opposite when a burn-in test is implemented, a wiring layer provided on the substrate, and a temperature sensor for measuring a temperature of the semiconductor wafer in the state here the semiconductor wafer is placing opposite on the substrate, wherein the wiring layer includes a wiring which is connected to the semiconductor wafer in the state where the semiconductor wafer is placing opposite on the substrate, and supplies a signal and a voltage for the burn-in test to the semiconductor wafer, and the temperature sensor is provided on the substrate in vicinity of the opposed-wafer surface.
    Type: Application
    Filed: July 5, 2006
    Publication date: January 11, 2007
    Inventors: Naomi Miyake, Minoru Sanada
  • Patent number: 6049147
    Abstract: The present invention provides a motor and a stator structure of the motor and an assembly method of the stator structure and a method of installing the motor. The stator structure of the motor contains a stator substrate having a double-layer structure of a printed circuit board and a magnetic plate jointed together at a plurality of calking sections, wherein a centroid is determined with respect to the plurality of calking sections on the printed circuit board, and a vacant area having no electric parts provided is determined nearby the centroid on the printed circuit board to allow the vacant area to be supported by a retainer of a calking jig.
    Type: Grant
    Filed: September 17, 1998
    Date of Patent: April 11, 2000
    Assignee: Victor Company of Japan, Ltd.
    Inventors: Minoru Sanada, Isamu Hashimoto
  • Patent number: 4742053
    Abstract: The invention relates to an antibiotic comprising a compound having the formula: ##STR1## wherein R.sup.1 is a straight chain, branched chain, or cyclic lower alkyl group which may be substituted by a carboxyl group, and R.sup.2 designates vicinal dihydroxyl groups or diacetoxy groups; or a pharmaceutically acceptable salt, physiologically hydrolyzable ester or solvate thereof.
    Type: Grant
    Filed: November 8, 1985
    Date of Patent: May 3, 1988
    Assignee: Banyu Pharmaceutical Co., Ltd.
    Inventors: Susumu Nakagawa, Ryosuke Ushijima, Eiichi Mano, Norikazu Ban, Minoru Sanada