Patents by Inventor Minoru Sasaki

Minoru Sasaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050144949
    Abstract: A waste heat recovery system of an engine has a cooling water circuit and a Rankine cycle. Cooling water is circulated between the engine and a radiator in the cooling water circuit. The Rankine cycle has a heater and an expansion device. The heater performs heat exchange between the cooling water heated by the engine and an operation fluid so as to heat the operation fluid in the Rankine cycle. The expansion device expands the heated operation fluid, so as to generate driving power. The heater is arranged in a bypass circuit so as to be in parallel with the radiator with respect to the cooling water flow. Thus, waste heat of the cooling water heated by the engine can be effectively recovered without reducing a cooling capacity of the radiator.
    Type: Application
    Filed: February 8, 2005
    Publication date: July 7, 2005
    Inventors: Shinichi Hamada, Minoru Sasaki, Atsushi Inaba
  • Publication number: 20040255586
    Abstract: A waste heat recovery system of an engine has a cooling water circuit and a Rankine cycle. Cooling water is circulated between the engine and a radiator in the cooling water circuit. The Rankine cycle has a heater and an expansion device. The heater performs heat exchange between the cooling water heated by the engine and an operation fluid so as to heat the operation fluid in the Rankine cycle. The expansion device expands the heated operation fluid, so as to generate driving power. The heater is arranged in a bypass circuit so as to be in parallel with the radiator with respect to the cooling water flow. Thus, waste heat of the cooling water heated by the engine can be effectively recovered without reducing a cooling capacity of the radiator.
    Type: Application
    Filed: June 21, 2004
    Publication date: December 23, 2004
    Inventors: Shinichi Hamada, Minoru Sasaki, Atsushi Inaba
  • Publication number: 20040237576
    Abstract: A radiator for a vapor-compression refrigerant cycle and a condenser for a Rankine cycle are integrated to construct a heat exchanger. The heat exchanger includes a core portion for performing a heat exchange, and is disposed to have a first function portion used as the radiator and a second function portion used as the condenser. A function ratio changing ratio includes a displacement member such as a plunger disposed in a header tank of the heat exchanger, and changes a ratio between the first function portion and the second function portion. For example, the displacement member partitions an inner space of the header tank into two space parts when both the vapor-compression refrigerant cycle and the Rankine cycle are operated, and does not partition the inner space when only one of the vapor-compression refrigerant cycle and the Rankine cycle is operated.
    Type: Application
    Filed: April 22, 2004
    Publication date: December 2, 2004
    Inventors: Minoru Sasaki, Atsushi Inaba, Takashi Yamanaka, Eiichi Torigoe
  • Publication number: 20040086124
    Abstract: To provide a cryptographic system capable of flexibly changing decryption authorization and preventing the action of a third person impersonating a user having the decryption authorization to improperly utilize the system.
    Type: Application
    Filed: October 17, 2003
    Publication date: May 6, 2004
    Inventor: Minoru Sasaki
  • Publication number: 20040007101
    Abstract: An anti-theft device is used with an attachment device used to attach a hubcap to a wheel of a vehicle or a rim to an axle of a vehicle. Such an attachment device may be a bolt or a nut. The anti-theft device has a receiving portion and a key portion. The receiving portion of the anti-theft device receives a head of the attachment device. The key portion has a key arrangement provided on thereon.
    Type: Application
    Filed: April 21, 2003
    Publication date: January 15, 2004
    Inventor: Minoru Sasaki
  • Publication number: 20030204727
    Abstract: Disclosed are an information embedding method and apparatus for embedding watermark data in programs and compressed data. The method includes generating encoded content by attaching an error correction code to content, and generating watermark-embedded encoded content by embedding watermark data in the encoded content that has been generated. The watermark data has such data length that the watermark data can be removed if decoding processing is executed using the error correction code. The original content can be obtained from the watermark-embedded encoded content by decoding processing based upon the error correction code that has been attached to the watermark-embedded encoded content.
    Type: Application
    Filed: April 24, 2002
    Publication date: October 30, 2003
    Inventor: Minoru Sasaki
  • Publication number: 20020135033
    Abstract: A micro-mirror for deflecting an incident light is disclosed, wherein the micro-mirror comprises: a mirror section for reflecting an incident light issued from a laser diode; a hinge section including a fixed section and a movable section each having a flat surface; and a drive section having a bi-morph structure made of two or more of materials having different heat expansion coefficient for deflecting said mirror section to change relative angle to said incident light.
    Type: Application
    Filed: March 7, 2002
    Publication date: September 26, 2002
    Inventors: Masaki Hara, Takuya Makino, Kazuhito Hori, Kazuhiro Hane, Minoru Sasaki
  • Patent number: 6404031
    Abstract: If a semiconductor device employing semiconductor light-receiving elements is disposed on a single optical axis, laser light which is incident on these light-receiving elements is interrupted by the semiconductor device, and it will be impossible to confirm as a whole that the alignment of a multiplicity of components disposed over a distance has been correctly adjusted. This problem is overcome by using a semiconductor light-receiving element with a structure which absorbs only some of a received laser light beam and which allows the greater part of the beam to be transmitted to its rear face.
    Type: Grant
    Filed: November 17, 1998
    Date of Patent: June 11, 2002
    Inventors: Kazuhiro Hane, Minoru Sasaki
  • Patent number: 6351536
    Abstract: A key used for deciphering ciphertext is safely transmitted, to establish simple encryption communication. A transmitter and a receiver are connected through a network such that they can communicate with each other. In the transmitter, plaintext is enciphered using a common key. Ciphertext, together with a key generation program in a public-key cryptosystem, is transmitted from the transmitter to the receiver. In the receiver, a pair of a public key and a secret key is generated in accordance with the key generation program, the public key is transmitted to the transmitter, and the secret key is held in the receiver. In the transmitter, the common key is enciphered using the public key transmitted from the receiver. An enciphered common key transmitted to the receiver is deciphered using the held secret key. The ciphertext is deciphered using the deciphered common key.
    Type: Grant
    Filed: September 29, 1998
    Date of Patent: February 26, 2002
    Inventor: Minoru Sasaki
  • Patent number: 6337486
    Abstract: An electron beam drawing process of high throughput, coping with the changes in static distortion and dynamic distortion of a lower layer exposure apparatus or an optical reduction exposure apparatus. At least two marks formed in each chip formed on a wafer are detected for a predetermined number of chips, and the relation between the shape distortion of each chip in the wafer plane and the wafer coordinates is determined from the positions of the detected marks and the designed positions of the marks by a statistical processing. Patterns are drawn in all chips while correcting the patterns to be drawn on the individual chips, by using the relation between the determined chip shape distortion and the wafer coordinates. As a result, the superposition exposure with the lower layer can be achieved with a high throughput and with a high accuracy without any manual adjustment.
    Type: Grant
    Filed: April 30, 2001
    Date of Patent: January 8, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Minoru Sasaki, Yuji Tange, Yutaka Hojyo, Kazuyoshi Oonuki, Hiroyuki Itoh
  • Publication number: 20010015413
    Abstract: An electron beam drawing process of high throughput, coping with the changes in static distortion and dynamic distortion of a lower layer exposure apparatus or an optical reduction exposure apparatus. At least two marks formed in each chip formed on a wafer are detected for a predetermined number of chips, and the relation between the shape distortion of each chip in the wafer plane and the wafer coordinates is determined from the positions of the detected marks and the designed positions of the marks by a statistical processing. Patterns are drawn in all chips while correcting the patterns to be drawn on the individual chips, by using the relation between the determined chip shape distortion and the wafer coordinates. As a result, the superposition exposure with the lower layer can be achieved with a high throughput and with a high accuracy without any manual adjustment.
    Type: Application
    Filed: April 30, 2001
    Publication date: August 23, 2001
    Applicant: Hitachi, Ltd.
    Inventors: Minoru Sasaki, Yuji Tange, Yutaka Hojyo, Kazuyoshi Oonuki, Hiroyuki Itoh
  • Patent number: 6246064
    Abstract: An electron beam drawing process of high throughput, coping with the changes in static distortion and dynamic distortion of a lower layer exposure apparatus or an optical reduction exposure apparatus. At least two marks formed in each chip formed on a wafer are detected for a predetermined number of chips, and the relation between the shape distortion of each chip in the wafer plane and the wafer coordinates is determined from the positions of the detected marks and the designed positions of the marks by a statistical processing. Patterns are drawn in all chips while correcting the patterns to be drawn on the individual chips, by using the relation between the determined chip shape distortion and the wafer coordinates. As a result, the superposition exposure with the lower layer can be with a high throughput and with a high accuracy without any manual adjustment.
    Type: Grant
    Filed: June 29, 2000
    Date of Patent: June 12, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Minoru Sasaki, Yuji Tange, Yutaka Hojyo, Kazuyoshi Oonuki, Hiroyuki Itoh
  • Patent number: 6127683
    Abstract: An electron beam drawing process of high throughput, coping with the changes in static distortion and dynamic distortion of a lower layer exposure apparatus or an optical reduction exposure apparatus. At least two marks formed in each chip formed on a wafer are detected for a predetermined number of chips, and the relation between the shape distortion of each chip in the wafer plane and the wafer coordinates is determined from the positions of the detected marks and the designed positions of the marks by a statistical processing. Patterns are drawn in all chips while correcting the patterns to be drawn on the individual chips, by using the relation between the determined chip shape distortion and the wafer coordinates. As a result, the superposition exposure with the lower layer can be achieved with a high throughput and with a high accuracy without any manual adjustment.
    Type: Grant
    Filed: September 15, 1999
    Date of Patent: October 3, 2000
    Assignee: Hitachi, Ltd.
    Inventors: Minoru Sasaki, Yuji Tange, Yutaka Hojyo, Kazuyoshi Oonuki, Hiroyuki Itoh
  • Patent number: 6100865
    Abstract: In a display apparatus, a switch circuit including transistors is turned off to isolate a scanning line driving circuit and scanning lines from each other, the output of the scanning line driving circuit is inspected by the output from a terminal of an inspection circuit for the scanning line driving circuit, and the switch circuit is turned on to supply the output of the scanning line driving circuit to the scanning lines to check for a disconnection or a shorting of any of the scanning lines in accordance with the presence or absence or the magnitude of the voltage change appearing across the scanning line inspection circuit.
    Type: Grant
    Filed: June 10, 1997
    Date of Patent: August 8, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Minoru Sasaki
  • Patent number: 6049321
    Abstract: A liquid crystal display includes a matrix array of liquid crystal pixels, data lines formed along columns of the pixels, TFTs assigned to the pixels for causing the data lines to be electrically connected to the pixels of a selected row, and a data line driver which drives the data lines and has a first video bus for transmitting analog pixel signals of the positive polarity for the pixels of one of odd and even columns in a selected row, a second video bus for transmitting analog pixel signals of the negative polarity for the pixels of the other one of the odd and even columns in the selected row, sample-hold units each assigned to adjacent two of the data lines to simultaneously sample-hold the pixel signals on the first and second video buses, and a shift register circuit for enabling the operations of the sample-hold units sequentially.
    Type: Grant
    Filed: September 25, 1997
    Date of Patent: April 11, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Minoru Sasaki
  • Patent number: 5972772
    Abstract: An electron beam drawing process of high throughput, coping with the changes in static distortion and dynamic distortion of a lower layer exposure apparatus or an optical reduction exposure apparatus. At least two marks formed in each chip formed on a wafer are detected for a predetermined number of chips, and the relation between the shape distortion of each chip in the wafer plane and the wafer coordinates is determined from the positions of the detected marks and the designed positions of the marks by a statistical processing. Patterns are drawn in all chips while correcting the patterns to be drawn on the individual chips, by using the relation between the determined chip shape distortion and the wafer coordinates. As a result, the superposition exposure with the lower layer can be achieved with a high throughput and with a high accuracy without any manual adjustment.
    Type: Grant
    Filed: September 3, 1997
    Date of Patent: October 26, 1999
    Assignees: Hitachi Ltd., Hitachi Instruments Engineering Co., Ltd.
    Inventors: Minoru Sasaki, Yuji Tange, Yutaka Hojyo, Kazuyoshi Oonuki, Hiroyuki Itoh
  • Patent number: 5870477
    Abstract: A plaintext file 41 is enciphered using a file key 44, to generate ciphertext 42. The file key 44 is enciphered using a secret key 47 and a management key 48, respectively, to form an enciphered key 1 (45) and an enciphered key 2 (46). An enciphered file 43 is produced from the ciphertext 42, the enciphered key 1 and the enciphered key 2. At the time of decryption, the enciphered key 1 is taken out from the enciphered file 43. The enciphered key 1 taken out is deciphered using a secret key 47, to obtain a file key 44. The ciphertext 42 is deciphered using the file key 44, to obtain the plaintext 41.
    Type: Grant
    Filed: March 29, 1996
    Date of Patent: February 9, 1999
    Assignee: Pumpkin House Incorporated
    Inventors: Minoru Sasaki, Hiroharu Yoshikawa
  • Patent number: 5623937
    Abstract: An object of the present device is to precisely lock the output of electrical stimulation pulses onto diastolic periods.An electrical stimulator comprises a pulse sensor, a systolic period pulse producing unit for producing a systolic signal using the pulse wave sensor, a signal oscillator for electrical stimulation production, an electrical stimulation pulse output unit for outputting electrical stimulation pulses according to the output signal of the signal oscillator for electrical stimulation production, and a gate for controlling the connection between the signal oscillator for electrical stimulation production and the electrical stimulation pulse output unit according to the systolic signal supplied by the systolic period signal producing unit.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: April 29, 1997
    Assignee: Kabushiki Kaisya Advance
    Inventor: Minoru Sasaki
  • Patent number: 5575809
    Abstract: An object of the present invention is to precisely lock the output of electrical stimulation pulses onto diastolic periods. An electrical stimulator comprises a pulse sensor, a systolic period pulse producing unit for producing a systolic signal using the pulse wave sensor, a signal oscillator for electrical stimulation production, an electrical stimulation pulse output unit for outputting electrical stimulation pulses according to the output signal of the signal oscillator for electrical stimulation production, and a gate for controlling the connection between the signal oscillator for electrical stimulation production and the electrical stimulation pulse output unit according to the systolic signal supplied by the systolic period signal producing unit.
    Type: Grant
    Filed: June 11, 1993
    Date of Patent: November 19, 1996
    Assignee: Kabushiki Kaisya Advance
    Inventor: Minoru Sasaki
  • Patent number: 5531775
    Abstract: The present invention provides an electric thermal treatment device that uses no battery, has a compact design, enables satisfactory thermotherapy, and completes charging quickly. The electric thermal treatment device comprises a heating unit including a charge storage, a heater that generates heat using current discharged from the charge storage, and an attachment that attaches the device to the skin, and a power supply unit for supplying a charge to the charge storage in the heating unit. The heating unit is electrically coupled with the power supply unit to receive charge. After being decoupled from the power supply unit, the heating unit is attached to the skin of human body and generates heat.
    Type: Grant
    Filed: July 5, 1994
    Date of Patent: July 2, 1996
    Assignee: Kabushiki Kaisya Advance
    Inventors: Minoru Sasaki, Sinichirou Watanabe