Patents by Inventor Minoru Senda
Minoru Senda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8593859Abstract: When an operational mode is shifted to a standby mode, a first transistor is brought into a conduction state by a control signal, and a word line is thereby clamped to a ground voltage. Further, a second transistor is brought into a non-conduction state, and supply of an internal power supply voltage to a word line driver is shut off. Subsequently, the supply of the internal power supply voltage is halted for saving electrical power. When the operational mode returns to a normal mode, the supply of the internal power supply voltage is started, and subsequently, the first transistor is brought into the non-conduction state by the control signal, and the second transistor is thereby brought into the conduction state.Type: GrantFiled: January 18, 2011Date of Patent: November 26, 2013Assignee: Renesas Electronics CorporationInventors: Takeshi Agari, Hirotoshi Sato, Kiyoyasu Akai, Minoru Senda, Hiroaki Nakai
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Publication number: 20110116321Abstract: When an operational mode is shifted to a standby mode, a first transistor is brought into a conduction state by a control signal, and a word line is thereby clamped to a ground voltage. Further, a second transistor is brought into a non-conduction state, and supply of an internal power supply voltage to a word line driver is shut off. Subsequently, the supply of the internal power supply voltage is halted for saving electrical power. When the operational mode returns to a normal mode, the supply of the internal power supply voltage is started, and subsequently, the first transistor is brought into the non-conduction state by the control signal, and the second transistor is thereby brought into the conduction state.Type: ApplicationFiled: January 18, 2011Publication date: May 19, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Takeshi AGARI, Hirotoshi Sato, Kiyoyasu Akai, Minoru Senda, Hiroaki Nakai
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Patent number: 7894292Abstract: When an operational mode is shifted to a standby mode, a first transistor is brought into a conduction state by a control signal, and a word line is thereby clamped to a ground voltage. Further, a second transistor is brought into a non-conduction state, and supply of an internal power supply voltage to a word line driver is shut off. Subsequently, the supply of the internal power supply voltage is halted for saving electrical power. When the operational mode returns to a normal mode, the supply of the internal power supply voltage is started, and subsequently, the first transistor is brought into the non-conduction state by the control signal, and the second transistor is thereby brought into the conduction state.Type: GrantFiled: January 27, 2009Date of Patent: February 22, 2011Assignee: Renesas Electronics CorporationInventors: Takeshi Agari, Hirotoshi Sato, Kiyoyasu Akai, Minoru Senda, Hiroaki Nakai
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Patent number: 7630239Abstract: The present invention provides a semiconductor device which comprises a plurality of memory cells which stores data therein based on threshold voltages thereof, a plurality of bit lines on which read signals based on the stored data of the memory cells appear respectively, a plurality of sense amplifiers which are respectively disposed corresponding to the bit lines and which respectively detect the read signals having appeared on the bit lines and output first and second signals respectively having logical levels different from one another from first and second nodes, based on the detected read signals, and a determination unit which determines, based on the first and second signals received from the first and second nodes of the sense amplifiers, whether the threshold voltages of the memory cells are normal.Type: GrantFiled: September 11, 2007Date of Patent: December 8, 2009Assignee: Renesas Technology Corp.Inventors: Minoru Senda, Jun Setogawa
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Publication number: 20090196115Abstract: When an operational mode is shifted to a standby mode, a first transistor is brought into a conduction state by a control signal, and a word line is thereby clamped to a ground voltage. Further, a second transistor is brought into a non-conduction state, and supply of an internal power supply voltage to a word line driver is shut off. Subsequently, the supply of the internal power supply voltage is halted for saving electrical power. When the operational mode returns to a normal mode, the supply of the internal power supply voltage is started, and subsequently, the first transistor is brought into the non-conduction state by the control signal, and the second transistor is thereby brought into the conduction state.Type: ApplicationFiled: January 27, 2009Publication date: August 6, 2009Inventors: Takeshi Agari, Hirotoshi Sato, Kiyoyasu Akai, Minoru Senda, Hiroaki Nakai
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Publication number: 20080175066Abstract: The present invention provides a semiconductor device which comprises a plurality of memory cells which stores data therein based on threshold voltages thereof, a plurality of bit lines on which read signals based on the stored data of the memory cells appear respectively, a plurality of sense amplifiers which are respectively disposed corresponding to the bit lines and which respectively detect the read signals having appeared on the bit lines and output first and second signals respectively having logical levels different from one another from first and second nodes, based on the detected read signals, and a determination unit which determines, based on the first and second signals received from the first and second nodes of the sense amplifiers, whether the threshold voltages of the memory cells are normal.Type: ApplicationFiled: September 11, 2007Publication date: July 24, 2008Inventors: Minoru Senda, Jun Setogawa
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Patent number: 7365578Abstract: In the present semiconductor device a positive, driving pump circuit is driven by an external power supply potential EXVDD (for example of 1.8V) to generate a positive voltage VPC (for example of 2.4V). A negative pump circuit for internal operation is driven by the positive voltage VPC to generate a negative voltage VNA (for example of ?9.2V) required in an erasure or similar internal operation for a word line. The negative pump circuit for internal operation can have a smaller number of stages of pump and hence consume a smaller area than when the circuit is driven by the external power supply voltage EXVDD (for example of 1.8V) as conventional.Type: GrantFiled: July 3, 2007Date of Patent: April 29, 2008Assignee: Renesas Technology Corp.Inventors: Minoru Senda, Kiyohiro Furutani, Taku Ogura, Shigehiro Kuge, Satoshi Kawasaki, Tadaaki Yamauchi
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Publication number: 20070285146Abstract: In the present semiconductor device a positive, driving pump circuit is driven by an external power supply potential EXVDD (for example of 1.8V) to generate a positive voltage VPC (for example of 2.4V). A negative pump circuit for internal operation is driven by the positive voltage VPC to generate a negative voltage VNA (for example of ?9.2V) required in an erasure or similar internal operation for a word line. The negative pump circuit for internal operation can have a smaller number of stages of pump and hence consume a smaller area than when the circuit is driven by the external power supply voltage EXVDD (for example of 1.8V) as conventional.Type: ApplicationFiled: July 3, 2007Publication date: December 13, 2007Applicant: RENESAS TECHNOLOGY CORP.Inventors: Minoru Senda, Kiyohiro Furutani, Taku Ogura, Shigehiro Kuge, Satoshi Kawasaki, Tadaaki Yamauchi
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Patent number: 7268612Abstract: In the present semiconductor device a positive, driving pump circuit is driven by an external power supply potential EXVDD (for example of 1.8V) to generate a positive voltage VPC (for example of 2.4V). A negative pump circuit for internal operation is driven by the positive voltage VPC to generate a negative voltage VNA (for example of ?9.2V) required in an erasure or similar internal operation for a word line. The negative pump circuit for internal operation can have a smaller number of stages of pump and hence consume a smaller area than when the circuit is driven by the external power supply voltage EXVDD (for example of 1.8V) as conventional.Type: GrantFiled: January 30, 2007Date of Patent: September 11, 2007Assignee: Renesas Technology Corp.Inventors: Minoru Senda, Kiyohiro Furutani, Taku Ogura, Shigehiro Kuge, Satoshi Kawasaki, Tadaaki Yamauchi
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Publication number: 20070120592Abstract: In the present semiconductor device a positive, driving pump circuit is driven by an external power supply potential EXVDD (for example of 1.8V) to generate a positive voltage VPC (for example of 2.4V). A negative pump circuit for internal operation is driven by the positive voltage VPC to generate a negative voltage VNA (for example of ?9.2V) required in an erasure or similar internal operation for a word line. The negative pump circuit for internal operation can have a smaller number of stages of pump and hence consume a smaller area than when the circuit is driven by the external power supply voltage EXVDD (for example of 1.8V) as conventional.Type: ApplicationFiled: January 30, 2007Publication date: May 31, 2007Applicant: Renesas Technology Corp.Inventors: Minoru Senda, Kiyohiro Furutani, Taku Ogura, Shigehiro Kuge, Satoshi Kawasaki, Tadaaki Yamauchi
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Patent number: 7180362Abstract: In the present semiconductor device a positive, driving pump circuit is driven by an external power supply potential EXVDD (for example of 1.8V) to generate a positive voltage VPC (for example of 2.4V). A negative pump circuit for internal operation is driven by the positive voltage VPC to generate a negative voltage VNA (for example of ?9.2V) required in an erasure or similar internal operation for a word line. The negative pump circuit for internal operation can have a smaller number of stages of pump and hence consume a smaller area than when the circuit is driven by the external power supply voltage EXVDD (for example of 1.8V) as conventional.Type: GrantFiled: September 15, 2004Date of Patent: February 20, 2007Assignee: Renesas Technology Corp.Inventors: Minoru Senda, Kiyohiro Furutani, Taku Ogura, Shigehiro Kuge, Satoshi Kawasaki, Tadaaki Yamauchi
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Patent number: 6927620Abstract: A semiconductor device includes a boosting circuit for supplying a power supply voltage during a standby state of the semiconductor device. The boosting circuit includes a charge pump circuit and first and second detection circuits for detecting an output voltage of the charge pump circuit. The second detection circuit is operated by a DC current greater than that of the first detection circuit, and is activated by an output (Vdet1) from the first detection circuit. The charge pump circuit is activated based on at least an output (Vdet2) from the second detection circuit.Type: GrantFiled: November 7, 2003Date of Patent: August 9, 2005Assignee: Renesas Technology Corp.Inventor: Minoru Senda
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Publication number: 20050057288Abstract: In the present semiconductor device a positive, driving pump circuit is driven by an external power supply potential EXVDD (for example of 1.8V) to generate a positive voltage VPC (for example of 2.4V). A negative pump circuit for internal operation is driven by the positive voltage VPC to generate a negative voltage VNA (for example of ?9.2V) required in an erasure or similar internal operation for a word line. The negative pump circuit for internal operation can have a smaller number of stages of pump and hence consume a smaller area than when the circuit is driven by the external power supply voltage EXVDD (for example of 1.8V) as conventional.Type: ApplicationFiled: September 15, 2004Publication date: March 17, 2005Inventors: Minoru Senda, Kiyohiro Furutani, Taku Ogura, Shigehiro Kuge, Satoshi Kawasaki, Tadaaki Yamauchi
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Publication number: 20040150463Abstract: A semiconductor device includes a boosting circuit for supplying a power supply voltage during a standby state of the semiconductor device. The boosting circuit includes a charge pump circuit and first and second detection circuits for detecting an output voltage of the charge pump circuit. The second detection circuit is operated by a DC current greater than that of the first detection circuit, and is activated by an output (Vdet1) from the first detection circuit. The charge pump circuit is activated based on at least an output (Vdet2) from the second detection circuit.Type: ApplicationFiled: November 7, 2003Publication date: August 5, 2004Applicant: RENESAS TECHNOLOGY CORP.Inventor: Minoru Senda
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Patent number: 6737906Abstract: In operation, a charge pumping circuit supplies negative charges to an internal voltage line so as to reduce a negative internal voltage. A voltage dividing circuit produces a control voltage according to the difference between a first positive voltage externally applied to a first input terminal in the test mode and the internal voltage. A comparison circuit operates the charge pumping circuit according to the comparison result between a second positive voltage externally applied to a second input terminal in the test mode and the control voltage. The second positive voltage is set according to a target value of the negative internal voltage.Type: GrantFiled: November 13, 2001Date of Patent: May 18, 2004Assignee: Renesas Technology Corp.Inventors: Minoru Senda, Masaki Tsukude
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Patent number: 6628559Abstract: The semiconductor memory device of the invention has a refresh timer for generating a refresh clock, a refresh executing circuit for sequentially refreshing a plurality of memory cells part by part on the basis of the cycle of the refresh clock, and a refreshing control circuit disposed between the refresh timer and the refresh executing circuit, for stopping transmission of the refresh clock from the refresh timer to the refresh executing circuit in a predetermined period during which the cycle of the refresh clock is easy to become unstable. With the configuration, an erroneous operation of the refresh executing circuit can be prevented.Type: GrantFiled: October 9, 2001Date of Patent: September 30, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tadayuki Shimizu, Masaki Tsukude, Minoru Senda
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Patent number: 6584013Abstract: A dynamic-type memory A, a non-volatile memory B and a static-type memory C are enclosed in one package. Separated from a first terminal supplying a power-supply potential to the memories A and B, a second terminal supplying a power-supply potential to the memory C is provided. By stopping the supply of the power-supply potential to the first terminal at stand-by, stand-by current of a semiconductor memory device can be reduced. Therefore, the semiconductor memory device having an increased memory capacity while reducing a mounting area and consumption current at stand-by can be provided.Type: GrantFiled: October 22, 2001Date of Patent: June 24, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Minoru Senda, Shinichi Kobayashi, Masaki Tsukude, Hirotoshi Sato, Tadayuki Shimizu
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Patent number: 6535441Abstract: A voltage supply circuit has a resistive element, a p-channel MOS transistor, and n-channel MOS transistors. The resistive element and the p-channel MOS transistor are connected in parallel between a power source node and a node. The n-channel MOS transistors are connected in series between the node and the ground node. The voltage supply circuit supplies a threshold voltage of the n-channel MOS transistor to the node connected to a cell Vcc line of a memory cell in response to a test mode signal TE of the H level, and supplies an external source voltage in response to a test mode signal of the L level. In such a manner, a memory cell having an abnormal current in a standby mode can be detected by an operation test.Type: GrantFiled: July 26, 2001Date of Patent: March 18, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Minoru Senda, Shigeki Ohbayashi
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Publication number: 20020175744Abstract: In operation, a charge pumping circuit supplies negative charges to an internal voltage line so as to reduce a negative internal voltage. A voltage dividing circuit produces a control voltage according to the difference between a first positive voltage externally applied to a first input terminal in the test mode and the internal voltage. A comparison circuit operates the charge pumping circuit according to the comparison result between a second positive voltage externally applied to a second input terminal in the test mode and the control voltage. The second positive voltage is set according to a target value of the negative internal voltage.Type: ApplicationFiled: November 13, 2001Publication date: November 28, 2002Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Minoru Senda, Masaki Tsukude
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Publication number: 20020159289Abstract: A dynamic-type memory A, a non-volatile memory B and a static-type memory C are enclosed in one package. Separated from a first terminal supplying a power-supply potential to the memories A and B, a second terminal supplying a power-supply potential to the memory C is provided. By stopping the supply of the power-supply potential to the first terminal at stand-by, stand-by current of a semiconductor memory device can be reduced. Therefore, the semiconductor memory device having an increased memory capacity while reducing a mounting area and consumption current at stand-by can be provided.Type: ApplicationFiled: October 22, 2001Publication date: October 31, 2002Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Minoru Senda, Shinichi Kobayashi, Masaki Tsukude, Hirotoshi Sato, Tadayuki Shimizu