Abstract: A displacement sensor includes first detection units that detect an amount of displacement of a same detection target, and are disposed such that detection surfaces for detecting the amount of displacement face each other; second detection units that detect an amount of displacement of the detection target which is the same as the detection target of the first detection units, and are disposed such that detection surfaces for detecting the amount of displacement face each other; and a lead frame including a main frame having one surface on which the first detection units are disposed and the other surface on which the second detection units are disposed, and a sub frame which is wire-bonded to electrodes provided on each detection surface of the first detection units and the pair of second detection units.

Abstract: An electronic component module includes: a first lead frame including a mounting portion on which a chip is mounted, a relay portion connected to an electrode portion of the chip by a lead wire, and a first lead portion connected to the relay portion; a second lead frame including a second lead portion connected to the first lead portion and having a thickness larger than that of the first lead frame; a first molded portion that covers the mounting portion and the relay portion in a state where the first lead portion protrudes; and a second molded portion that covers a connecting portion between the first lead portion and the second lead portion in a state where the first lead portion and the second lead portion protrude.

Abstract: A displacement sensor includes: first detection units that detect an amount of displacement of a same detection target, and are disposed such that detection surfaces for detecting the amount of displacement face each other; second detection units that detect an amount of displacement of the detection target which is the same as the detection target of the first detection units, and are disposed such that detection surfaces for detecting the amount of displacement face each other; and a lead frame including a main frame having one surface on which the first detection units are disposed and the other surface on which the second detection units are disposed, and a sub frame which is wire-bonded to electrodes provided on each detection surface of the first detection units and the pair of second detection units.

Abstract: Provided is a semiconductor device which is compact and highly reliable. The semiconductor device includes a multi-gauge strip leadframe having a thick portion and thin portions thinner than the thick portion, a chip mounting portion on which a semiconductor chip is mounted, a relaying portion connected via a lead wire to a connecting portion provided in the semiconductor chip, and connecting terminals connected to the relaying portion. In the multi-gage strip leadframe, the thick portion is formed at a center portion in a Y direction of this multi-gauge strip leadframe, with a predetermined width along an X direction perpendicular to the Y direction, and the thin portions are formed on opposed sides of the thick portion in the X direction. The chip mounting portion is formed in the thick portion and the relaying portion is formed in the thick portion separately from the chip mounting portion. The connecting terminals are formed in the thin portions.

Abstract: Provided is a rational arrangement of an electronic component package that tightly keeps a connecting state of a lead member to a conductive pad of a substrate. The electronic component package includes a substrate having a conductive pad and mounting an electronic component, a lead member electrically conducted to the conductive pad, and a molded portion in which the above members are embedded. The lead member includes an inner conductor having bifurcated end portions and a unitary portion formed integral therewith. The inner conductor and a part of the unitary portion which are embedded in the molded portion are curved in protrusive or sunken manner relative to an imaginary plane extending along the surface of the substrate.

Abstract: A memory card has a wiring board, four memory chips stacked on a main surface of the wiring board, and a controller chip and an interposer mounted on a surface of the memory chip of the uppermost layer. The memory chips are stacked on the surface of the wiring board so that their long sides are directed in the same direction as that of the long side of the wiring board. The memory chip of the lowermost layer is mounted on the wiring board in a dislocated manner by a predetermined distance in a direction toward a front end of the memory card so as not to overlap the pads of the wiring board. The three memory chips stacked on the memory chip of the lowermost layer are disposed so that their short sides on which pads are formed are located at the front end of the memory card.

Abstract: A memory card has a wiring board, four memory chips stacked on a main surface of the wiring board, and a controller chip and an interposer mounted on a surface of the memory chip of the uppermost layer. The memory chips are stacked on the surface of the wiring board so that their long sides are directed in the same direction as that of the long side of the wiring board. The memory chip of the lowermost layer is mounted on the wiring board in a dislocated manner by a predetermined distance in a direction toward a front end of the memory card so as not to overlap the pads of the wiring board. The three memory chips stacked on the memory chip of the lowermost layer are disposed so that their short sides on which pads are formed are located at the front end of the memory card.

Abstract: A technology enabling reduction of the size of a semiconductor device including a micro and a power MOSFET is provided. The semiconductor device is obtained by single packaging a first semiconductor chip with a micro formed therein and second semiconductor chips with a power MOSFET formed therein. This makes it possible to reduce the size of the semiconductor device as compared with cases where a first semiconductor chip with a micro formed therein and second semiconductor chips with a power MOSFET formed therein are separately packaged.

Abstract: A memory card has a wiring board, four memory chips stacked on a main surface of the wiring board, and a controller chip and an interposer mounted on a surface of the memory chip of the uppermost layer. The memory chips are stacked on the surface of the wiring board so that their long sides are directed in the same direction as that of the long side of the wiring board. The memory chip of the lowermost layer is mounted on the wiring board in a dislocated manner by a predetermined distance in a direction toward a front end of the memory card so as not to overlap the pads of the wiring board. The three memory chips stacked on the memory chip of the lowermost layer are disposed so that their short sides on which pads are formed are located at the front end of the memory card.

Abstract: In a POP type semiconductor device comprising a second semiconductor package as an upper package stacked on a first semiconductor package as a lower package, a plurality of main surface-side lands formed on a first wiring substrate of the first semiconductor package are disposed distributively on both sides of a chip mounting region as a boundary positioned at a central part of a main surface of the first wiring substrate, thus permitting the adoption of a through molding method. Consequently, a first sealing body formed on the main surface of the first wiring substrate in the first semiconductor package as a lower package extends from one second side of the first wiring substrate toward a central part of the other second side of the same substrate.

Abstract: Reduction of the size of and enhancement of the reliability, mounting strength, and mounting reliability of a semiconductor module are achieved. The semiconductor module includes: a wiring substrate; an electronic component placed over the upper surface of the wiring substrate; an electronic component placed over the under surface of the wiring substrate; a lead placed over the under surface of the wiring substrate; and encapsulation resin covering the under surface of the wiring substrate including the electronic component and the lead. The lead includes: a first portion coupled to an electrode pad via a joining material; a second portion bent from the first portion; and a third portion bent from the second portion. The third portion is positioned closer to the peripheral edge portion side of the under surface of the wiring substrate than the first portion. At the same time, the third portion is arranged at a position farther from the under surface of the wiring substrate than the first portion.

Abstract: A memory card has a wiring board, four memory chips stacked on a main surface of the wiring board, and a controller chip and an interposer mounted on a surface of the memory chip of the uppermost layer. The memory chips are stacked on the surface of the wiring board so that their long sides are directed in the same direction as that of the long side of the wiring board. The memory chip of the lowermost layer is mounted on the wiring board in a dislocated manner by a predetermined distance in a direction toward a front end of the memory card so as not to overlap the pads of the wiring board. The three memory chips stacked on the memory chip of the lowermost layer are disposed so that their short sides on which pads are formed are located at the front end of the memory card.

Abstract: A semiconductor device with semiconductor chips stacked thereon is provided. The semiconductor device is reduced in size and thickness. In a first memory chip and a second memory chip, first pads of the first memory chip located at a lower stage and hidden by the second memory chip located at an upper stage are drawn out by re-wiring lines, whereby the first pads projected and exposed from the overlying second memory chip and second pads of the second memory chip can be coupled together through wires. Further, a microcomputer chip and third pads formed on re-wiring lines are coupled together through wires over the second memory chip, whereby wire coupling of the stacked memory chips can be done without intervention of a spacer.

Abstract: A memory card has a wiring board, four memory chips stacked on a main surface of the wiring board, and a controller chip and an interposer mounted on a surface of the memory chip of the uppermost layer. The memory chips are stacked on the surface of the wiring board so that their long sides are directed in the same direction as that of the long side of the wiring board. The memory chip of the lowermost layer is mounted on the wiring board in a dislocated manner by a predetermined distance in a direction toward a front end of the memory card so as not to overlap the pads of the wiring board. The three memory chips stacked on the memory chip of the lowermost layer are disposed so that their short sides on which pads are formed are located at the front end of the memory card.

Abstract: A memory card has a wiring board, four memory chips stacked on a main surface of the wiring board, and a controller chip and an interposer mounted on a surface of the memory chip of the uppermost layer. The memory chips are stacked on the surface of the wiring board so that their long sides are directed in the same direction as that of the long side of the wiring board. The memory chip of the lowermost layer is mounted on the wiring board in a dislocated manner by a predetermined distance in a direction toward a front end of the memory card so as not to overlap the pads of the wiring board. The three memory chips stacked on the memory chip of the lowermost layer are disposed so that their short sides on which pads are formed are located at the front end of the memory card.

Abstract: A technology enabling reduction of the size of a semiconductor device including a micro and a power MOSFET is provided. The semiconductor device is obtained by single packaging a first semiconductor chip with a micro formed therein and second semiconductor chips with a power MOSFET formed therein. This makes it possible to reduce the size of the semiconductor device as compared with cases where a first semiconductor chip with a micro formed therein and second semiconductor chips with a power MOSFET formed therein are separately packaged.

Abstract: A semiconductor device with semiconductor chips stacked thereon is provided. The semiconductor device is reduced in size and thickness. In a first memory chip and a second memory chip, first pads of the first memory chip located at a lower stage and hidden by the second memory chip located at an upper stage are drawn out by re-wiring lines, whereby the first pads projected and exposed from the overlying second memory chip and second pads of the second memory chip can be coupled together through wires. Further, a microcomputer chip and third pads formed on re-wiring lines are coupled together through wires over the second memory chip, whereby wire coupling of the stacked memory chips can be done without intervention of a spacer.

Abstract: Reduction of the size of and enhancement of the reliability, mounting strength, and mounting reliability of a semiconductor module are achieved. The semiconductor module includes: a wiring substrate; an electronic component placed over the upper surface of the wiring substrate; an electronic component placed over the under surface of the wiring substrate; a lead placed over the under surface of the wiring substrate; and encapsulation resin covering the under surface of the wiring substrate including the electronic component and the lead. The lead includes: a first portion coupled to an electrode pad via a joining material; a second portion bent from the first portion; and a third portion bent from the second portion. The third portion is positioned closer to the peripheral edge portion side of the under surface of the wiring substrate than the first portion. At the same time, the third portion is arranged at a position farther from the under surface of the wiring substrate than the first portion.

Abstract: A semiconductor device with semiconductor chips stacked thereon is provided. The semiconductor device is reduced in size and thickness. In a first memory chip and a second memory chip, first pads of the first memory chip located at a lower stage and hidden by the second memory chip located at an upper stage are drawn out by re-wiring lines, whereby the first pads projected and exposed from the overlying second memory chip and second pads of the second memory chip can be coupled together through wires. Further, a microcomputer chip and third pads formed on re-wiring lines are coupled together through wires over the second memory chip, whereby wire coupling of the stacked memory chips can be done without intervention of a spacer.

Abstract: A semiconductor device has operation modes selectable through the control by a second microcomputer (113). In a first mode, an operation of a memory controller (105) responding to a memory card command from a memory card interface terminal and an operation of a first microcomputer (106) responding to an IC card command from an IC card interface terminal are separately performed. In a second mode, the first microcomputer operates in response to the IC card command from the IC card interface terminal. In a third mode, the memory controller and the first microcomputer operate in response to an undefined IC card command from the IC card interface terminal. In a fourth mode, the memory controller and the first microcomputer operate in response to the memory card command from the memory card interface terminal. Convenience of the semiconductor device having an IC card function and a memory card function is improved.