Patents by Inventor Minoru Shinohara

Minoru Shinohara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240302881
    Abstract: A communication adapter that can notify occurrence of power supply interruption to external management device in response to power supply interruption is provided. The communication adapter includes a power storage configured to receive power supply from an external device and store power, a communication unit configured to receive power supply from the power storage, and a control unit capable of communicating with an external management device via the communication unit. A capacity of the power storage for the control unit to communicate with the external management device has variable lower limit. Lower limit of the capacity of the power storage while the power storage is receiving power supply from the external device is first capacity value. Lower limit of the capacity of the power storage in a case of power supply to the power storage from the external device being interrupted is second capacity value lower than first capacity value.
    Type: Application
    Filed: June 23, 2022
    Publication date: September 12, 2024
    Inventors: Noriyuki SHINOHARA, Toshiyuki TANAKA, Minoru CHIHARA
  • Publication number: 20240297520
    Abstract: A communication adapter capable of performing communication even in a case where power supply from an external device has ceased is provided. The communication adapter includes a power storage configured to receive power supplied from an external device and store the power, a communication unit configured to receive power supplied from the power storage, a control unit configured to communicate with an external management device via the communication unit, a first power supply line through which the power supplied from the external device goes to the control unit, thereby bypassing the power storage, and a second power supply line through which the power supplied from the power storage goes to the control unit.
    Type: Application
    Filed: June 23, 2022
    Publication date: September 5, 2024
    Inventors: Toshiyuki TANAKA, Noriyuki SHINOHARA, Minoru CHIHARA, Yoshimasa NAKAYAMA
  • Patent number: 10288448
    Abstract: A displacement sensor includes first detection units that detect an amount of displacement of a same detection target, and are disposed such that detection surfaces for detecting the amount of displacement face each other; second detection units that detect an amount of displacement of the detection target which is the same as the detection target of the first detection units, and are disposed such that detection surfaces for detecting the amount of displacement face each other; and a lead frame including a main frame having one surface on which the first detection units are disposed and the other surface on which the second detection units are disposed, and a sub frame which is wire-bonded to electrodes provided on each detection surface of the first detection units and the pair of second detection units.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: May 14, 2019
    Assignee: AISIN SEIKI KABUSHIKI KAISHA
    Inventor: Minoru Shinohara
  • Publication number: 20180286791
    Abstract: An electronic component module includes: a first lead frame including a mounting portion on which a chip is mounted, a relay portion connected to an electrode portion of the chip by a lead wire, and a first lead portion connected to the relay portion; a second lead frame including a second lead portion connected to the first lead portion and having a thickness larger than that of the first lead frame; a first molded portion that covers the mounting portion and the relay portion in a state where the first lead portion protrudes; and a second molded portion that covers a connecting portion between the first lead portion and the second lead portion in a state where the first lead portion and the second lead portion protrude.
    Type: Application
    Filed: March 15, 2018
    Publication date: October 4, 2018
    Applicant: AISIN SEIKI KABUSHIKI KAISHA
    Inventors: Minoru SHINOHARA, Hiroya SEIKE
  • Publication number: 20180080798
    Abstract: A displacement sensor includes: first detection units that detect an amount of displacement of a same detection target, and are disposed such that detection surfaces for detecting the amount of displacement face each other; second detection units that detect an amount of displacement of the detection target which is the same as the detection target of the first detection units, and are disposed such that detection surfaces for detecting the amount of displacement face each other; and a lead frame including a main frame having one surface on which the first detection units are disposed and the other surface on which the second detection units are disposed, and a sub frame which is wire-bonded to electrodes provided on each detection surface of the first detection units and the pair of second detection units.
    Type: Application
    Filed: September 15, 2017
    Publication date: March 22, 2018
    Applicant: AISIN SEIKI KABUSHIKI KAISHA
    Inventor: Minoru SHINOHARA
  • Publication number: 20160293530
    Abstract: Provided is a semiconductor device which is compact and highly reliable. The semiconductor device includes a multi-gauge strip leadframe having a thick portion and thin portions thinner than the thick portion, a chip mounting portion on which a semiconductor chip is mounted, a relaying portion connected via a lead wire to a connecting portion provided in the semiconductor chip, and connecting terminals connected to the relaying portion. In the multi-gage strip leadframe, the thick portion is formed at a center portion in a Y direction of this multi-gauge strip leadframe, with a predetermined width along an X direction perpendicular to the Y direction, and the thin portions are formed on opposed sides of the thick portion in the X direction. The chip mounting portion is formed in the thick portion and the relaying portion is formed in the thick portion separately from the chip mounting portion. The connecting terminals are formed in the thin portions.
    Type: Application
    Filed: October 21, 2014
    Publication date: October 6, 2016
    Applicant: AISIN SEIKI KABUSHIKI KAISHA
    Inventors: Minoru SHINOHARA, Naoki NAKAMURA
  • Publication number: 20160284632
    Abstract: Provided is a rational arrangement of an electronic component package that tightly keeps a connecting state of a lead member to a conductive pad of a substrate. The electronic component package includes a substrate having a conductive pad and mounting an electronic component, a lead member electrically conducted to the conductive pad, and a molded portion in which the above members are embedded. The lead member includes an inner conductor having bifurcated end portions and a unitary portion formed integral therewith. The inner conductor and a part of the unitary portion which are embedded in the molded portion are curved in protrusive or sunken manner relative to an imaginary plane extending along the surface of the substrate.
    Type: Application
    Filed: October 20, 2014
    Publication date: September 29, 2016
    Applicant: AISIN SEIKI KABUSHIKI KAISHA
    Inventors: Minoru SHINOHARA, Naoki Nakamura
  • Patent number: 9377825
    Abstract: A memory card has a wiring board, four memory chips stacked on a main surface of the wiring board, and a controller chip and an interposer mounted on a surface of the memory chip of the uppermost layer. The memory chips are stacked on the surface of the wiring board so that their long sides are directed in the same direction as that of the long side of the wiring board. The memory chip of the lowermost layer is mounted on the wiring board in a dislocated manner by a predetermined distance in a direction toward a front end of the memory card so as not to overlap the pads of the wiring board. The three memory chips stacked on the memory chip of the lowermost layer are disposed so that their short sides on which pads are formed are located at the front end of the memory card.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: June 28, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Minoru Shinohara, Makoto Araki, Michiaki Sugiyama
  • Publication number: 20140347809
    Abstract: A memory card has a wiring board, four memory chips stacked on a main surface of the wiring board, and a controller chip and an interposer mounted on a surface of the memory chip of the uppermost layer. The memory chips are stacked on the surface of the wiring board so that their long sides are directed in the same direction as that of the long side of the wiring board. The memory chip of the lowermost layer is mounted on the wiring board in a dislocated manner by a predetermined distance in a direction toward a front end of the memory card so as not to overlap the pads of the wiring board. The three memory chips stacked on the memory chip of the lowermost layer are disposed so that their short sides on which pads are formed are located at the front end of the memory card.
    Type: Application
    Filed: June 5, 2014
    Publication date: November 27, 2014
    Inventors: Minoru SHINOHARA, Makoto ARAKI, Michiaki SUGIYAMA
  • Patent number: 8779575
    Abstract: A technology enabling reduction of the size of a semiconductor device including a micro and a power MOSFET is provided. The semiconductor device is obtained by single packaging a first semiconductor chip with a micro formed therein and second semiconductor chips with a power MOSFET formed therein. This makes it possible to reduce the size of the semiconductor device as compared with cases where a first semiconductor chip with a micro formed therein and second semiconductor chips with a power MOSFET formed therein are separately packaged.
    Type: Grant
    Filed: December 26, 2010
    Date of Patent: July 15, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Minoru Shinohara
  • Patent number: 8754534
    Abstract: A memory card has a wiring board, four memory chips stacked on a main surface of the wiring board, and a controller chip and an interposer mounted on a surface of the memory chip of the uppermost layer. The memory chips are stacked on the surface of the wiring board so that their long sides are directed in the same direction as that of the long side of the wiring board. The memory chip of the lowermost layer is mounted on the wiring board in a dislocated manner by a predetermined distance in a direction toward a front end of the memory card so as not to overlap the pads of the wiring board. The three memory chips stacked on the memory chip of the lowermost layer are disposed so that their short sides on which pads are formed are located at the front end of the memory card.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: June 17, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Minoru Shinohara, Makoto Araki, Michiaki Sugiyama
  • Patent number: 8648453
    Abstract: In a POP type semiconductor device comprising a second semiconductor package as an upper package stacked on a first semiconductor package as a lower package, a plurality of main surface-side lands formed on a first wiring substrate of the first semiconductor package are disposed distributively on both sides of a chip mounting region as a boundary positioned at a central part of a main surface of the first wiring substrate, thus permitting the adoption of a through molding method. Consequently, a first sealing body formed on the main surface of the first wiring substrate in the first semiconductor package as a lower package extends from one second side of the first wiring substrate toward a central part of the other second side of the same substrate.
    Type: Grant
    Filed: October 27, 2009
    Date of Patent: February 11, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Minoru Shinohara, Tomibumi Inoue, Seiichiro Tsukui
  • Patent number: 8432033
    Abstract: Reduction of the size of and enhancement of the reliability, mounting strength, and mounting reliability of a semiconductor module are achieved. The semiconductor module includes: a wiring substrate; an electronic component placed over the upper surface of the wiring substrate; an electronic component placed over the under surface of the wiring substrate; a lead placed over the under surface of the wiring substrate; and encapsulation resin covering the under surface of the wiring substrate including the electronic component and the lead. The lead includes: a first portion coupled to an electrode pad via a joining material; a second portion bent from the first portion; and a third portion bent from the second portion. The third portion is positioned closer to the peripheral edge portion side of the under surface of the wiring substrate than the first portion. At the same time, the third portion is arranged at a position farther from the under surface of the wiring substrate than the first portion.
    Type: Grant
    Filed: August 6, 2010
    Date of Patent: April 30, 2013
    Assignee: Renesas Electronics Corporation
    Inventor: Minoru Shinohara
  • Patent number: 8319352
    Abstract: A memory card has a wiring board, four memory chips stacked on a main surface of the wiring board, and a controller chip and an interposer mounted on a surface of the memory chip of the uppermost layer. The memory chips are stacked on the surface of the wiring board so that their long sides are directed in the same direction as that of the long side of the wiring board. The memory chip of the lowermost layer is mounted on the wiring board in a dislocated manner by a predetermined distance in a direction toward a front end of the memory card so as not to overlap the pads of the wiring board. The three memory chips stacked on the memory chip of the lowermost layer are disposed so that their short sides on which pads are formed are located at the front end of the memory card.
    Type: Grant
    Filed: June 12, 2011
    Date of Patent: November 27, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Minoru Shinohara, Makoto Araki, Michiaki Sugiyama
  • Patent number: 8237267
    Abstract: A semiconductor device with semiconductor chips stacked thereon is provided. The semiconductor device is reduced in size and thickness. In a first memory chip and a second memory chip, first pads of the first memory chip located at a lower stage and hidden by the second memory chip located at an upper stage are drawn out by re-wiring lines, whereby the first pads projected and exposed from the overlying second memory chip and second pads of the second memory chip can be coupled together through wires. Further, a microcomputer chip and third pads formed on re-wiring lines are coupled together through wires over the second memory chip, whereby wire coupling of the stacked memory chips can be done without intervention of a spacer.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: August 7, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Minoru Shinohara
  • Publication number: 20110233788
    Abstract: A memory card has a wiring board, four memory chips stacked on a main surface of the wiring board, and a controller chip and an interposer mounted on a surface of the memory chip of the uppermost layer. The memory chips are stacked on the surface of the wiring board so that their long sides are directed in the same direction as that of the long side of the wiring board. The memory chip of the lowermost layer is mounted on the wiring board in a dislocated manner by a predetermined distance in a direction toward a front end of the memory card so as not to overlap the pads of the wiring board. The three memory chips stacked on the memory chip of the lowermost layer are disposed so that their short sides on which pads are formed are located at the front end of the memory card.
    Type: Application
    Filed: June 12, 2011
    Publication date: September 29, 2011
    Inventors: MINORU SHINOHARA, Makoto Araki, Michiaki Sugiyama
  • Patent number: 7989960
    Abstract: A memory card has a wiring board, four memory chips stacked on a main surface of the wiring board, and a controller chip and an interposer mounted on a surface of the memory chip of the uppermost layer. The memory chips are stacked on the surface of the wiring board so that their long sides are directed in the same direction as that of the long side of the wiring board. The memory chip of the lowermost layer is mounted on the wiring board in a dislocated manner by a predetermined distance in a direction toward a front end of the memory card so as not to overlap the pads of the wiring board. The three memory chips stacked on the memory chip of the lowermost layer are disposed so that their short sides on which pads are formed are located at the front end of the memory card.
    Type: Grant
    Filed: February 4, 2009
    Date of Patent: August 2, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Minoru Shinohara, Makoto Araki, Michiaki Sugiyama
  • Publication number: 20110156229
    Abstract: A technology enabling reduction of the size of a semiconductor device including a micro and a power MOSFET is provided. The semiconductor device is obtained by single packaging a first semiconductor chip with a micro formed therein and second semiconductor chips with a power MOSFET formed therein. This makes it possible to reduce the size of the semiconductor device as compared with cases where a first semiconductor chip with a micro formed therein and second semiconductor chips with a power MOSFET formed therein are separately packaged.
    Type: Application
    Filed: December 26, 2010
    Publication date: June 30, 2011
    Inventor: Minoru SHINOHARA
  • Publication number: 20110140285
    Abstract: A semiconductor device with semiconductor chips stacked thereon is provided. The semiconductor device is reduced in size and thickness. In a first memory chip and a second memory chip, first pads of the first memory chip located at a lower stage and hidden by the second memory chip located at an upper stage are drawn out by re-wiring lines, whereby the first pads projected and exposed from the overlying second memory chip and second pads of the second memory chip can be coupled together through wires. Further, a microcomputer chip and third pads formed on re-wiring lines are coupled together through wires over the second memory chip, whereby wire coupling of the stacked memory chips can be done without intervention of a spacer.
    Type: Application
    Filed: February 8, 2011
    Publication date: June 16, 2011
    Inventor: MINORU SHINOHARA
  • Publication number: 20110037170
    Abstract: Reduction of the size of and enhancement of the reliability, mounting strength, and mounting reliability of a semiconductor module are achieved. The semiconductor module includes: a wiring substrate; an electronic component placed over the upper surface of the wiring substrate; an electronic component placed over the under surface of the wiring substrate; a lead placed over the under surface of the wiring substrate; and encapsulation resin covering the under surface of the wiring substrate including the electronic component and the lead. The lead includes: a first portion coupled to an electrode pad via a joining material; a second portion bent from the first portion; and a third portion bent from the second portion. The third portion is positioned closer to the peripheral edge portion side of the under surface of the wiring substrate than the first portion. At the same time, the third portion is arranged at a position farther from the under surface of the wiring substrate than the first portion.
    Type: Application
    Filed: August 6, 2010
    Publication date: February 17, 2011
    Inventor: Minoru SHINOHARA