Abstract: A resist composition which generates an acid by exposure and whose solubility in a developing solution changes by the action of an acid. The resist composition contains a high-molecular-weight compound having a constitutional unit represented by General Formula (a0-1), and a high-molecular-weight compound having a constitutional unit represented by General Formula (f01-1) and a constitutional unit including an acid-dissociable group represented by General Formula (f02-r-1).

Abstract: Disclosed herein is an apparatus that includes a fuse array circuit including a plurality of fuse sets each assigned to a corresponding one of a plurality of fuse addresses and configured to operatively store a fuse data, and a first circuit configured to generate and sequentially update a fuse address to sequentially read the fuse data from the plurality of fuse sets. The first circuit is configured to change a frequency of updating the fuse address based on a first signal.

Abstract: Disclosed herein is an apparatus that includes a fuse array circuit including a plurality of fuse sets each assigned to a corresponding one of a plurality of fuse addresses and configured to operatively store a fuse data, and a first circuit configured to generate and sequentially update a fuse address to sequentially read the fuse data from the plurality of fuse sets. The first circuit is configured to change a frequency of updating the fuse address based on a first signal.

Abstract: An example fuse error detection circuit configured to receive a first data set from a fuse array during a first fuse data broadcast and to encode the first data set to provide first signature data. The fuse error detection circuit is further configured to receive a second data set from the fuse array during a second fuse data broadcast and to encode the second data set to provide second signature data. The fuse error detection circuit is further configured to compare the first signature data and the second signature data and to provide a match indication having a value based on the comparison between the first signature data and the second signature data.

Abstract: Compensating for offsets in buffers and related systems, methods, and devices are disclosed. An apparatus includes buffers, control circuitry, and fuses. Each of the buffers includes an output and an offset adjustment input. Each of the buffers is controllable to adjust a direct current offset of an output voltage potential responsive to an offset adjustment code provided to the offset adjustment input. The control circuitry includes sets of offset latches. The offset adjustment input of each of the buffers is operably coupled to a different one of the sets of offset latches. Each set of offset latches is configured to provide the offset adjustment code to the offset adjustment input of a corresponding buffer. The fuses are configured to provide the offset adjustment code to each of a subset of the sets of offset latches.

Abstract: Memory devices are disclosed. A memory device may include a number of fuses and a number of transmit lines configured to transmit data from the number of fuses. The memory device may also include a number of monitoring circuits. Each monitoring circuit of the number of monitoring circuits is coupled to a transmit line of the number of transmit lines. Each monitoring circuit comprises logic configured to receive the data from the number fuses via the transmit line. The logic is further configured to generate a result responsive to the data and indicative of pass/fail status of the transmit line. Associated methods and systems are also disclosed.

Abstract: Compensating for offsets in buffers and related systems, methods, and devices are disclosed. An apparatus includes buffers, control circuitry, and fuses. Each of the buffers includes an output and an offset adjustment input. Each of the buffers is controllable to adjust a direct current offset of an output voltage potential responsive to an offset adjustment code provided to the offset adjustment input. The control circuitry includes sets of offset latches. The offset adjustment input of each of the buffers is operably coupled to a different one of the sets of offset latches. Each set of offset latches is configured to provide the offset adjustment code to the offset adjustment input of a corresponding buffer. The fuses are configured to provide the offset adjustment code to each of a subset of the sets of offset latches.

Abstract: Compensating for offsets in buffers and related systems, methods, and devices are disclosed. An apparatus includes buffers, control circuitry, and fuses. Each of the buffers includes an output and an offset adjustment input. Each of the buffers is controllable to adjust a direct current offset of an output voltage potential responsive to an offset adjustment code provided to the offset adjustment input. The control circuitry includes sets of offset latches. The offset adjustment input of each of the buffers is operably coupled to a different one of the sets of offset latches. Each set of offset latches is configured to provide the offset adjustment code to the offset adjustment input of a corresponding buffer. The fuses are configured to provide the offset adjustment code to each of a subset of the sets of offset latches.

Abstract: An example fuse error detection circuit configured to receive a first data set from a fuse array during a first fuse data broadcast and to encode the first data set to provide first signature data. The fuse error detection circuit is further configured to receive a second data set from the fuse array during a second fuse data broadcast and to encode the second data set to provide second signature data. The fuse error detection circuit is further configured to compare the first signature data and the second signature data and to provide a match indication having a value based on the comparison between the first signature data and the second signature data.

Abstract: Apparatuses and methods for transmitting fuse data from fuse arrays to latches are described. An example apparatus includes: a plurality of fuse arrays, each fuse array of the plurality of fuse arrays being configured to store input data; a fuse circuit that receives the input data and provides the input data on a bus; and a plurality of redundancy latch circuits coupled to the bus, including a plurality of pointers and a plurality of latches associated with the plurality of corresponding pointers that load data on the bus. The fuse circuit may control loading of the input data by controlling a location of a pointer among the plurality of corresponding pointers responsive to the input data.

Abstract: Apparatuses and methods for transmitting fuse data from fuse arrays to latches are described. An example apparatus includes: a plurality of fuse arrays, each fuse array of the plurality of fuse arrays being configured to store input data; a fuse circuit that receives the input data and provides the input data on a bus; and a plurality of redundancy latch circuits coupled to the bus, including a plurality of pointers and a plurality of latches associated with the plurality of corresponding pointers that load data on the bus. The fuse circuit may control loading of the input data by controlling a location of a pointer among the plurality of corresponding pointers responsive to the input data.

Abstract: Apparatuses and methods for transmitting fuse data from fuse arrays to latches are described. An example apparatus includes: a plurality of fuse arrays, each fuse array of the plurality of fuse arrays being configured to store input data; a fuse circuit that receives the input data and provides the input data on a bus; and a plurality of redundancy latch circuits coupled to the bus, including a plurality of pointers and a plurality of latches associated with the plurality of corresponding pointers that load data on the bus. The fuse circuit may control loading of the input data by controlling a location of a pointer among the plurality of corresponding pointers responsive to the input data.

Abstract: Apparatuses and methods for transmitting fuse data from fuse arrays to latches are described. An example apparatus includes: a plurality of fuse arrays, each fuse array of the plurality of fuse arrays being configured to store input data; a fuse circuit that receives the input data and provides the input data on a bus; and a plurality of redundancy latch circuits coupled to the bus, including a plurality of pointers and a plurality of latches associated with the plurality of corresponding pointers that load data on the bus. The fuse circuit may control loading of the input data by controlling a location of a pointer among the plurality of corresponding pointers responsive to the input data.

Abstract: Apparatuses and methods for transmitting fuse data from fuse arrays to latches are described. An example apparatus includes: a plurality of fuse arrays, each fuse array of the plurality of fuse arrays being configured to store input data; a fuse circuit that receives the input data and provides the input data on a bus; and a plurality of redundancy latch circuits coupled to the bus, including a plurality of pointers and a plurality of latches associated with the plurality of corresponding pointers that load data on the bus. The fuse circuit may control loading of the input data by controlling a location of a pointer among the plurality of corresponding pointers responsive to the input data.

Abstract: A female-side connector having a lock mechanism for obtaining a favorable fastening force constantly. The female-side connector includes a central axis of a root in a male screw portion of a female-side lock portion that is screwed together with a female screw portion of a male-side lock portion in a male-side connector that intersects at a predetermined angle relative to a central axis of a thread.

Abstract: [Problem to be Solved] To provide a female-side connector having a lock mechanism which could obtain a favorable fastening force constantly. [Solution] In a female-side connector 10, a central axis 13 of a root 15 in a male screw portion 12 of a female-side lock portion 41 screwing together with a female screw portion 23 of a male-side lock portion 42 in a male-side connector 20 intersects at a predetermined angle relative to a central axis 14 of a thread 16.