Patents by Inventor Minoru Takeno

Minoru Takeno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040184809
    Abstract: A double-ring optical wavelength multiplex network is disclosed, which includes multiple optical transmission apparatuses that can reduce the unit cost of initially installing a small optical network while providing the flexibility to expand. For multiplexed optical signals arriving at a node, the optical transmission apparatus “drops” selected wavelengths for local delivery and “passes” others for continued transmission on the network. For optical signals originating (“added”) at the node, the optical transmission apparatus wavelength multiplexes the “added” signals with the “passing” signals for transmission on the network. For “added” signals, the optical transmission apparatus blocks “passing” signals of the same wavelength.
    Type: Application
    Filed: January 27, 2004
    Publication date: September 23, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Hideyuki Miyata, Hiroaki Tomofuji, Hiroshi Onaka, Minoru Takeno
  • Patent number: 5132570
    Abstract: A programmable logic array with an extended logical scale includes a logic array part (21) which carries out a logic operation provided by a logic circuit for an input signal and provides an output signal indicative of an operation result. The logic array part includes semiconductor switching elements (22) provided at programmable logic array intersecting points, the logic operation of the logic circuit being changed by logic setting data supplied to the semiconductor switching elements. The structure further includes a storage circuit (23) which stores sets of logic setting data, and a setting circuit (24) which sequentially selects one of the sets of logic setting dated stored in the storage circuit and supplies the logic array part with the selected set of logic setting data.
    Type: Grant
    Filed: April 30, 1990
    Date of Patent: July 21, 1992
    Assignee: Fujitsu Limited
    Inventors: Hideki Shutou, Fumihiro Suenaga, Minoru Takeno
  • Patent number: 5025176
    Abstract: A peak level detection circuit provided with a peak holding unit used for determining the threshold level for discrimination of the logics "1" and "0" of the received data from the peak level of the received data signals, wherein even if after a first input pulse train with a peak level of V.sub.in1 is received, a second input pulse train having a peak level of V.sub.in2 lower than V.sub.in1 is received, it is made possible to immediately discriminate the logics "1" and "0" of the second input pulse train by detecting the appearance of the second input pulse train, then immediately pulling down the V.sub.in1 which is held.
    Type: Grant
    Filed: January 30, 1990
    Date of Patent: June 18, 1991
    Assignee: Fujitsu Limited
    Inventor: Minoru Takeno