Patents by Inventor Minoru Togo

Minoru Togo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180181913
    Abstract: Provided is a feature for generating a recommended shelf allocation indicating the state in which products are displayed, the recommended shelf allocation including a state in which specified products are displayed in more effective positions. The present invention is provided with: a generation means for generating a plurality of shelf allocation candidates indicating the state in which a plurality of products including the specified products are displayed on product shelves; a prediction means for predicting the sales of the specified products for the plurality of shelf allocation candidates, on the basis of the positional relationships among the products displayed on the product shelf, and of the relationships with sales of the products; and a selection means for selecting the shelf allocation candidates on the basis of the results of the predictions.
    Type: Application
    Filed: June 7, 2016
    Publication date: June 28, 2018
    Inventors: Kyota HIGA, Takami SATO, Kota IWAMOTO, Yaeko YONEZAWA, Minoru TOGO
  • Patent number: 8878709
    Abstract: Disclosed herein is a semiconductor integrated circuit including: line buffers; an alpha channel first selector; an alpha channel digital-to-analog converter; a beta channel digital-to-analog converter; a redundant digital-to-analog converter; an alpha channel second selector; a beta channel second selector; an alpha channel amplifier; and a beta channel amplifier.
    Type: Grant
    Filed: June 16, 2010
    Date of Patent: November 4, 2014
    Assignee: Sony Corporation
    Inventors: Kenji Hyodo, Takashi Ichirizuka, Takuya Kimoto, Minoru Togo
  • Publication number: 20110001765
    Abstract: Disclosed herein is a semiconductor integrated circuit including: line buffers; an alpha channel first selector; an alpha channel digital-to-analog converter; a beta channel digital-to-analog converter; a redundant digital-to-analog converter; an alpha channel second selector; a beta channel second selector; an alpha channel amplifier; and a beta channel amplifier.
    Type: Application
    Filed: June 16, 2010
    Publication date: January 6, 2011
    Applicant: Sony Corporation
    Inventors: Kenji Hyodo, Takashi Ichirizuka, Takuya Kimoto, Minoru Togo
  • Publication number: 20100182299
    Abstract: A semiconductor integrated circuit is disclosed which includes: a first D/A converter; a second D/A converter; an amplifier configured to amplify an output of the first D/A converter; an operational amplifier configured to input an output of the second D/A converter; and a selector configured to effect switchover between a normal mode and a test mode, the normal mode being a mode in which the operational amplifier is caused to function as an amplifier for amplifying the output of the second D/A converter, the test mode being a mode in which the operational amplifier is caused to function as a comparator for comparing the output of the second D/A converter with the output of the first D/A converter.
    Type: Application
    Filed: December 3, 2009
    Publication date: July 22, 2010
    Applicant: Sony Corporation
    Inventors: Kenji Hyoudou, Takashi Ichirizuka, Takuya Kimoto, Minoru Togo