Patents by Inventor Minoru Ueki
Minoru Ueki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7054705Abstract: A semiconductor device manufacturing system is provided in which chip position information is read without removing resin from a package so that the cause of a failure can be quickly identified and removed and the yield of chips can be rapidly improved. A replacement address reading device reads redundancy addresses from a semiconductor device which is determined as faulty in a test performed after the semiconductor device has been sealed into a package. A chip position analyzing device estimates, from the combination of these redundancy addresses, a lot number, a wafer number and a chip number of the faulty semiconductor device. A failure distribution mapping device maps the distribution of faulty chips in each wafer in the lot based on these numbers thus obtained. A failure cause determining device identifies which manufacturing device or processing step has caused the failures in the wafer process based on the above distribution.Type: GrantFiled: January 15, 2002Date of Patent: May 30, 2006Assignee: NEC Electronics CorporationInventors: Sumio Ogawa, Minoru Ueki, Shinichi Hara
-
Publication number: 20020059012Abstract: A semiconductor device manufacturing system is provided in which chip position information is read without removing resin from a package so that the cause of a failure can be quickly identified and removed and the yield of chips can be rapidly improved. A replacement address reading device reads redundancy addresses from a semiconductor device which is determined as faulty in a test performed after the semiconductor device has been sealed into a package. A chip position analyzing device estimates, from the combination of these redundancy addresses, a lot number, a wafer number and a chip number of the faulty semiconductor device. A failure distribution mapping device maps the distribution of faulty chips in each wafer in the lot based on these numbers thus obtained. A failure cause determining device identifies which manufacturing device or processing step has caused the failures in the wafer process based on the above distribution.Type: ApplicationFiled: January 15, 2002Publication date: May 16, 2002Applicant: NEC CORPORATIONInventors: Sumio Ogawa, Minoru Ueki, Shinichi Hara
-
Publication number: 20020059010Abstract: A semiconductor device manufacturing system is provided in which chip position information is read without removing resin from a package so that the cause of a failure can be quickly identified and removed and the yield of chips can be rapidly improved. A replacement address reading device reads redundancy addresses from a semiconductor device which is determined as faulty in a test performed after the semiconductor device has been sealed into a package. A chip position analyzing device estimates, from the combination of these redundancy addresses, a lot number, a wafer number and a chip number of the faulty semiconductor device. A failure distribution mapping device maps the distribution of faulty chips in each wafer in the lot based on these numbers thus obtained. A failure cause determining device identifies which manufacturing device or processing step has caused the failures in the wafer process based on the above distribution.Type: ApplicationFiled: January 15, 2002Publication date: May 16, 2002Applicant: NEC CORPORATIONInventors: Sumio Ogawa, Minoru Ueki, Shinichi Hara
-
Patent number: 6349240Abstract: A semiconductor device manufacturing system is provided in which chip position information is read without removing resin from a package so that the cause of a failure can be quickly identified and removed and the yield of chips can be rapidly improved. A replacement address reading device reads redundancy addresses from a semiconductor device which is determined as faulty in a test performed after the semiconductor device has been sealed into a package. A chip position analyzing device estimates, from the combination of these redundancy addresses, a lot number, a wafer number and a chip number of the faulty semiconductor device. A failure distribution mapping device maps the distribution of faulty chips in each wafer in the lot based on these numbers thus obtained. A failure cause determining device identifies which manufacturing device or processing step has caused the failures in the wafer process based on the above distribution.Type: GrantFiled: March 23, 2001Date of Patent: February 19, 2002Assignee: NEC CorporationInventors: Sumio Ogawa, Minoru Ueki, Shinichi Hara
-
Publication number: 20010026949Abstract: A semiconductor device manufacturing system is provided in which chip position information is read without removing resin from a package so that the cause of a failure can be quickly identified and removed and the yield of chips can be rapidly improved. A replacement address reading device reads redundancy addresses from a semiconductor device which is determined as faulty in a test performed after the semiconductor device has been sealed into a package. A chip position analyzing device estimates, from the combination of these redundancy addresses, a lot number, a wafer number and a chip number of the faulty semiconductor device. A failure distribution mapping device maps the distribution of faulty chips in each wafer in the lot based on these numbers thus obtained. A failure cause determining device identifies which manufacturing device or processing step has caused the failures in the wafer process based on the above distribution.Type: ApplicationFiled: March 23, 2001Publication date: October 4, 2001Inventors: Sumio Ogawa, Minoru Ueki, Shinichi Hara
-
Patent number: 6222606Abstract: Premising a duplex imaging apparatus having an image carrier provided with a plurality of image carrying regions, the image deterioration phenomenon (i.e., the so-called “oil ghost phenomenon”), as might otherwise accompany the local transfer of a releasing agent from a fixing unit to the image carrier, is effectively avoided.Type: GrantFiled: July 26, 1999Date of Patent: April 24, 2001Assignee: Fuji Xerox Co., Ltd.Inventors: Takashi Fuchiwaki, Akihisa Maruyama, Yasutomo Ishii, Katsuya Takenouchi, Keitaro Sonoguchi, Yasutaka Naito, Yasuyuki Kobayashi, Yoko Shimomura, Kazuhiko Miyazato, Shigehiko Haseba, Minoru Ueki, Satoshi Matsuzaka
-
Patent number: 6173136Abstract: Image deterioration (so-called oil ghost) due to local transfer of a release agent from a fuser to an intermediate transfer body is effectively prevented. The fuser has a pair of fixing members, a release supply mechanism, an interlocking mechanism, and an interlocking control mechanism. The fixing members are in contact with each other and roll over each other, thus nipping a sheet. The fixing members fix unfixed images on the sheet. The release agent supply mechanism is mounted to at least the fixing member located on the surface of the sheet carrying an unfixed image. The release agent supply mechanism supplies a release agent to this fixing member at a constant rate. The interlocking mechanism interlocks the fixing members and release agent supply mechanism with each other such that the fixing members are kept in contact with each other and roll over each other and that a release agent is supplied to the fixing members.Type: GrantFiled: August 3, 1999Date of Patent: January 9, 2001Assignee: Fuji Xerox Co., Ltd.Inventors: Takashi Fuchiwaki, Akihisa Maruyama, Yasutomo Ishii, Katsuya Takenouchi, Keitaro Sonoguchi, Yasutaka Naito, Yasuyuki Kobayashi, Yoko Shimomura, Kazuhiko Miyazato, Shigehiko Haseba, Minoru Ueki, Satoshi Matsuzaka