Patents by Inventor Minoru Yamagiwa

Minoru Yamagiwa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7337423
    Abstract: Established is a mask pattern correcting technique for reducing the load to a mask CAD process and for ensuring the minimum dimension defined in an OPC process. A method comprises the steps of: measuring a line width of a mask pattern; extracting edges where the line width of the mask pattern is smaller than a predetermined dimension; generating a central geometrical object having a predetermined width relative to the center between the edges where the line width is smaller than the predetermined dimension; and replacing the portion of the mask pattern where the line width is smaller than the predetermined dimension with the central geometrical object. As a result, the mask pattern line width is changed into the predetermined with dimension of the central geometrical object. This reduces notably the number of geometrical object calculating steps that had been performed for each value of dimension on the basis of a correction table in the prior art, and thereby shortens the mask CAD processing time.
    Type: Grant
    Filed: February 17, 2004
    Date of Patent: February 26, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Minoru Yamagiwa, Tadashi Tanimoto, Akio Misaka, Reiko Hinogami
  • Publication number: 20040243967
    Abstract: Reduction in labor of the operations for evaluating the amount of retrogression of end portions in a line pattern, and the simplification of the CAD processing for a mask are achieved. A semiconductor design layout pattern formation method is provided concerning a layout pattern on a wafer, wherein the designed wire lines do not have the same pitch, and wherein a dummy graphic pattern having no relation to wiring is formed in a non-wired region of the layout pattern so that the interval between the dummy graphic pattern and the adjacent wiring line becomes equal to the intervals of wiring lines. It becomes possible to make uniform the pitch of the end portions of lines in the design layout pattern on the wafer, so that the dispersion in the change of the form (retrogression) of the end portions of the lines can be restricted.
    Type: Application
    Filed: May 24, 2004
    Publication date: December 2, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Minoru Yamagiwa, Tadashi Tanimoto, Akio Misaka, Reiko Hinogami
  • Publication number: 20040191644
    Abstract: Established is a mask pattern correcting technique for reducing the load to a mask CAD process and for ensuring the minimum dimension defined in an OPC process. A method comprises the steps of: measuring a line width of a mask pattern; extracting edges where the line width of the mask pattern is smaller than a predetermined dimension; generating a central geometrical object having a predetermined width relative to the center between the edges where the line width is smaller than the predetermined dimension; and replacing the portion of the mask pattern where the line width is smaller than the predetermined dimension with the central geometrical object. As a result, the mask pattern line width is changed into the predetermined with dimension of the central geometrical object. This reduces notably the number of geometrical object calculating steps that had been performed for each value of dimension on the basis of a correction table in the prior art, and thereby shortens the mask CAD processing time.
    Type: Application
    Filed: February 17, 2004
    Publication date: September 30, 2004
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Minoru Yamagiwa, Tadashi Tanimoto, Akio Misaka, Reiko Hinogami