Abstract: A method for processing a takt at a station includes: obtaining takt data of each station within a preset time period, and determining a takt boxplot of each station according to the takt data; obtaining a material blocking time, a material shortage time and a failure time in each takt, determining an effective takt of each station based on the takt data, the material blocking time, the material shortage time and the failure time, and determining an effective takt mode; obtaining planning takt data of each station, generating a station takt wall station based on the takt boxplot, the effective takt mode and the planning takt data; determining a takt fluctuation status and a bottleneck of each station according to the station takt wall. A system for processing a takt at a station, an apparatus, and a storage medium are also disclosed.

Abstract: A floating-point data precision conversion method includes determining a bit width of a second mantissa field based on a coded value of a first exponent field. The floating-point data precision method further includes determining a reserved coded value and a discarded coded value in a first mantissa field. The floating-point data precision method further includes, if the coded value of the first exponent field is greater than or equal to a first preset threshold, performing a rounding operation on the reserved coded value based on a coded value that starts from a most significant bit and whose bit width is a preset bit width in the discarded coded value, to obtain a coded value of the second mantissa field.

Abstract: The present disclosure relates to floating-point data precision conversion methods and apparatuses. One example method includes determining a first bit width and a first coded value of the prefix code field, a first bit width and a first coded value of the second exponent field, and a first bit width of a second mantissa field based on a first coded value of a first exponent field, determining a to-be-retained coded value and a to-be-discarded coded value in a first mantissa field, where the to-be-retained coded value includes a coded value that starts from a most significant bit in the first mantissa field and whose bit width is the same as the first bit width of the second mantissa field, and performing a rounding operation on the to-be-retained coded value based on the to-be-discarded coded value to obtain a first coded value of the second mantissa field.

Abstract: A method for processing a takt at a station includes: obtaining takt data of each station within a preset time period, and determining a takt boxplot of each station according to the takt data; obtaining a material blocking time, a material shortage time and a failure time in each takt, determining an effective takt of each station based on the takt data, the material blocking time, the material shortage time and the failure time, and determining an effective takt mode; obtaining planning takt data of each station, generating a station takt wall station based on the takt boxplot, the effective takt mode and the planning takt data; determining a takt fluctuation status and a bottleneck of each station according to the station takt wall. A system for processing a takt at a station, an apparatus, and a storage medium are also disclosed.

Abstract: An adaptive search method includes: receiving a search condition set comprising target hardware platform information, network structure information of a source neural network, and one or more evaluation metrics; performing a training process on a to-be-trained super network based on a training dataset to obtain a trained super network, by extending a network structure of the source neural network; and performing a subnet search process on the trained super network based on the one or more evaluation metrics to obtain network structure information of a target neural network, which represents the target neural network and an evaluation result of the target neural network running on a target hardware platform is better than an evaluation result of the source neural network running on the target hardware platform.

Abstract: This disclosure provides a liquid crystal display panel. The liquid crystal display panel comprises: a first substrate and a second substrate arranged oppositely, a plurality of main spacers located between the first substrate and the second substrate for supporting cell gap of the liquid crystal display panel, a plurality of auxiliary spacers located between the first substrate and the second substrate, and a plurality of pressure sensing electrodes in one-to-one correspondence with the plurality of auxiliary spacers; wherein a height of the auxiliary spacer is smaller than a height of the main spacer; a material of the auxiliary spacer is a piezoelectric material. This disclosure also discloses a manufacturing method of the liquid crystal display panel and a display device comprising the liquid crystal display panel.

Abstract: This disclosure provides a liquid crystal display panel. The liquid crystal display panel comprises: a first substrate and a second substrate arranged oppositely, a plurality of main spacers located between the first substrate and the second substrate for supporting cell gap of the liquid crystal display panel, a plurality of auxiliary spacers located between the first substrate and the second substrate, and a plurality of pressure sensing electrodes in one-to-one correspondence with the plurality of auxiliary spacers; wherein a height of the auxiliary spacer is smaller than a height of the main spacer; a material of the auxiliary spacer is a piezoelectric material. This disclosure also discloses a manufacturing method of the liquid crystal display panel and a display device comprising the liquid crystal display panel.

Abstract: The present disclosure relates to the field of display technologies, and especially discloses a backlight device and a method for manufacturing the same. The backlight device includes a backlight source, a light guide plate, a reflective layer, an optical adhesive layer and an outcoupling structure. Specifically, in the backlight device, the reflective layer and the light guide plate are located on opposite sides of the backlight source respectively.

Abstract: This disclosure relates to a field-effect transistor and a production method thereof, an array substrate and a production method thereof, and a display panel. The production method comprises: forming an active layer on a substrate; forming a gate electrode insulating layer on the active layer to define a gate electrode area as well as a source electrode area and a drain electrode area located on two sides of the gate electrode area on the active layer; applying a gate electrode layer to cover surfaces of the active layer and the gate electrode insulating layer; patterning the gate electrode layer to form a first contact electrode, a second contact electrode, and a gate electrode, wherein the first contact electrode is located on the source electrode area, the second contact electrode is located on the drain electrode area, and the gate electrode is located on the gate electrode insulating layer.

Abstract: The present disclosure relates to the field of display technologies, and especially discloses a backlight device and a method for manufacturing the same. The backlight device includes a backlight source, a light guide plate, a reflective layer, an optical adhesive layer and an outcoupling structure. Specifically, in the backlight device, the reflective layer and the light guide plate are located on opposite sides of the backlight source respectively.

Abstract: This disclosure relates to a field-effect transistor and a production method thereof, an array substrate and a production method thereof, and a display panel. The production method comprises: forming an active layer on a substrate; forming a gate electrode insulating layer on the active layer to define a gate electrode area as well as a source electrode area and a drain electrode area located on two sides of the gate electrode area on the active layer; applying a gate electrode layer to cover surfaces of the active layer and the gate electrode insulating layer; patterning the gate electrode layer to form a first contact electrode, a second contact electrode, and a gate electrode, wherein the first contact electrode is located on the source electrode area, the second contact electrode is located on the drain electrode area, and the gate electrode is located on the gate electrode insulating layer.