Patents by Inventor Minseung Yoon
Minseung Yoon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11937497Abstract: Provided is an organic light-emitting device including: an anode; a cathode provided to face the anode; and organic material layers including a light emitting layer disposed between the anode and the cathode, wherein the light emitting layer, one or more layers of the organic material layers disposed between the anode and the light emitting layer, and one or more layers from among the organic material layers disposed between the cathode and the light emitting layer, each include one or more compounds each composed of sp3 carbon as a center, the light emitting layer includes a host including one or more anthracene-based compounds, and among organic materials included in the organic material layers, the bandgap energy (Ebg) of each of the organic materials except for a dopant compound is 3 eV or more.Type: GrantFiled: November 6, 2019Date of Patent: March 19, 2024Assignee: LG Chem, Ltd.Inventors: Jae Seung Ha, Minseung Chun, Woochul Lee, Sujeong Geum, Hongsik Yoon
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Publication number: 20240006328Abstract: An interposer includes a base layer including a first surface and a second surface that are opposite to each other. An interconnect structure is disposed on the first surface. The interconnect structure includes a metal interconnect pattern and an insulating layer surrounding the metal interconnect pattern. A first lower protection layer is disposed on the second surface. A plurality of lower conductive pads is disposed on the first lower protection layer. A plurality of through electrodes penetrates the base layer and the first lower protection layer. The plurality of through electrodes electrically connects the metal interconnect pattern of the interconnect structure to the lower conductive pads. At least one of the insulating layer and the first lower protection layer has compressive stress. A thickness of the first lower protection layer is in a range of about 13% to about 30% of a thickness of the insulating layer.Type: ApplicationFiled: September 11, 2023Publication date: January 4, 2024Inventors: Yukyung PARK, Minseung YOON, Yunseok CHOI
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Patent number: 11784131Abstract: An interposer includes a base layer including a first surface and a second surface that are opposite to each other. An interconnect structure is disposed on the first surface. The interconnect structure includes a metal interconnect pattern and an insulating layer surrounding the metal interconnect pattern. A first lower protection layer is disposed on the second surface. A plurality of lower conductive pads is disposed on the first lower protection layer. A plurality of through electrodes penetrates the base layer and the first lower protection layer. The plurality of through electrodes electrically connects the metal interconnect pattern of the interconnect structure to the lower conductive pads. At least one of the insulating layer and the first lower protection layer has compressive stress. A thickness of the first lower protection layer is in a range of about 13% to about 30% of a thickness of the insulating layer.Type: GrantFiled: February 1, 2021Date of Patent: October 10, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Yukyung Park, Minseung Yoon, Yunseok Choi
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Publication number: 20230111854Abstract: Provided is a semiconductor package, including a first redistribution substrate, a first semiconductor chip on the first redistribution substrate, first bumps between the first redistribution substrate and the first semiconductor chip, a conductive structure on the first redistribution substrate and spaced apart from the first semiconductor chip, a second redistribution substrate on the first semiconductor chip, second bumps between the first semiconductor chip and the second redistribution substrate, a second semiconductor chip on the second redistribution substrate, a first mold layer between the first redistribution substrate and the second redistribution substrate, and on the first semiconductor chip, and a second mold layer on the second redistribution substrate and the second semiconductor chip, and spaced apart from the first mold layer.Type: ApplicationFiled: June 28, 2022Publication date: April 13, 2023Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: JU-IL CHOI, UN-BYOUNG KANG, MINSEUNG YOON, YONGHOE CHO, JEONGGI JIN, YUN SEOK CHOI
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Publication number: 20220301958Abstract: A semiconductor package includes a circuit board mounting a first semiconductor chip and a second semiconductor chip laterally separated by an intermediate space, an underfill including an extended portion protruding upward into the intermediate space, a surface modification layer on opposing side surfaces of the first semiconductor chip and the second semiconductor chip, wherein wettability of the underfill with respect to the surface modification layer is less than wettability of the underfill with respect to the side surfaces of the first semiconductor chip and the second semiconductor chip, and a molding member on the upper surface of the circuit board, covering an upper surface of the extended portion of the underfill, and surrounding the first semiconductor chip and the second semiconductor chip.Type: ApplicationFiled: November 26, 2021Publication date: September 22, 2022Inventors: SUNGWOO PARK, SOOHYUN NAM, HYUNJUNG SONG, MINSEUNG YOON
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Publication number: 20210391269Abstract: An interposer includes a base layer including a first surface and a second surface that are opposite to each other. An interconnect structure is disposed on the first surface. The interconnect structure includes a metal interconnect pattern and an insulating layer surrounding the metal interconnect pattern. A first lower protection layer is disposed on the second surface. A plurality of lower conductive pads is disposed on the first lower protection layer. A plurality of through electrodes penetrates the base layer and the first lower protection layer. The plurality of through electrodes electrically connects the metal interconnect pattern of the interconnect structure to the lower conductive pads. At least one of the insulating layer and the first lower protection layer has compressive stress. A thickness of the first lower protection layer is in a range of about 13% to about 30% of a thickness of the insulating layer.Type: ApplicationFiled: February 1, 2021Publication date: December 16, 2021Inventors: Yukyung PARK, Minseung YOON, Yunseok CHOI
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Patent number: 9196505Abstract: In a semiconductor device, an organic insulation pattern is disposed between first and second rerouting patterns. The organic insulation pattern may absorb the physical stress that occurs when the first and second rerouting patterns expand under heat. Since the organic insulation pattern is disposed between the first and second rerouting patterns, insulating properties can be increased relative to a semiconductor device in which a semiconductor pattern is disposed between rerouting patterns. Also, since a seed layer pattern is disposed between the first and second rerouting patterns and the organic insulation pattern and between the substrate and the organic insulation pattern, the adhesive strength of the first and second rerouting patterns is enhanced. This also reduces any issues with delamination. Also, the seed layer pattern prevents the metal that forms the rerouting pattern from being diffused to the organic insulation pattern.Type: GrantFiled: May 28, 2013Date of Patent: November 24, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Un-Byoung Kang, Kwang-Chul Choi, Jung-Hwan Kim, Tae Hong Min, Hojin Lee, Minseung Yoon
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Publication number: 20130260551Abstract: In a semiconductor device, an organic insulation pattern is disposed between first and second rerouting patterns. The organic insulation pattern may absorb the physical stress that occurs when the first and second rerouting patterns expand under heat. Since the organic insulation pattern is disposed between the first and second rerouting patterns, insulating properties can be increased relative to a semiconductor device in which a semiconductor pattern is disposed between rerouting patterns. Also, since a seed layer pattern is disposed between the first and second rerouting patterns and the organic insulation pattern and between the substrate and the organic insulation pattern, the adhesive strength of the first and second rerouting patterns is enhanced. This also reduces any issues with delamination. Also, the seed layer pattern prevents the metal that forms the rerouting pattern from being diffused to the organic insulation pattern.Type: ApplicationFiled: May 28, 2013Publication date: October 3, 2013Applicant: Samsung Electronics Co., Ltd.Inventors: Un-Byoung Kang, Kwang-chul Choi, Jung-Hwan Kim, Tae Hong Min, Hojin Lee, Minseung Yoon
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Patent number: 8450856Abstract: In a semiconductor device, an organic insulation pattern is disposed between first and second rerouting patterns. The organic insulation pattern may absorb the physical stress that occurs when the first and second rerouting patterns expand under heat. Since the organic insulation pattern is disposed between the first and second rerouting patterns, insulating properties can be increased relative to a semiconductor device in which a semiconductor pattern is disposed between rerouting patterns. Also, since a seed layer pattern is disposed between the first and second rerouting patterns and the organic insulation pattern and between the substrate and the organic insulation pattern, the adhesive strength of the first and second rerouting patterns is enhanced. This also reduces any issues with delamination. Also, the seed layer pattern prevents the metal that forms the rerouting pattern from being diffused to the organic insulation pattern.Type: GrantFiled: September 22, 2011Date of Patent: May 28, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Un-Byoung Kang, Kwang-chul Choi, Jung-Hwan Kim, Tae Hong Min, Hojin Lee, Minseung Yoon
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Publication number: 20120153498Abstract: In a semiconductor device, an organic insulation pattern is disposed between first and second rerouting patterns. The organic insulation pattern may absorb the physical stress that occurs when the first and second rerouting patterns expand under heat. Since the organic insulation pattern is disposed between the first and second rerouting patterns, insulating properties can be increased relative to a semiconductor device in which a semiconductor pattern is disposed between rerouting patterns. Also, since a seed layer pattern is disposed between the first and second rerouting patterns and the organic insulation pattern and between the substrate and the organic insulation pattern, the adhesive strength of the first and second rerouting patterns is enhanced. This also reduces any issues with delamination. Also, the seed layer pattern prevents the metal that forms the rerouting pattern from being diffused to the organic insulation pattern.Type: ApplicationFiled: September 22, 2011Publication date: June 21, 2012Inventors: Un-Byoung Kang, Kwang-chul Choi, Jung-Hwan Kim, Tae Hong Min, Hojin Lee, Minseung Yoon
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Publication number: 20120049349Abstract: Provided is a semiconductor chip including a back side insulation structure. The semiconductor chip may include a semiconductor layer including an active surface and an inactive surface facing each other; the insulating layer includes a first surface adjacent to the inactive surface and a second surface facing the first surface. The insulating layer is disposed on the inactive surface of the semiconductor layer. A penetrating electrode fills a hole penetrating the semiconductor layer and the insulating layer. The through electrode comprises a protrusive portion protruding from the second surface of the insulating layer.Type: ApplicationFiled: July 7, 2011Publication date: March 1, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ho-Jin LEE, Donghyeon JANG, Hogeon SONG, SeYoung JEONG, Minseung YOON, Jung-Hwan KIM
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Publication number: 20110318917Abstract: Through-Silicon-Via (TSV) structures can be provided by forming a conductive via through a substrate extending from an upper surface of the substrate to a backside surface of the substrate, that is opposite the upper surface, and having a conductive protective layer comprising Ni and/or Co formed at a bottom of the conductive via. A polymer insulating layer can be formed on the backside surface that is separate from the substrate and in contact with the conductive protective layer.Type: ApplicationFiled: June 17, 2011Publication date: December 29, 2011Inventors: Minseung Yoon, Namseog Kim, Pyoungwan Kim, Keumhee Ma, Chajea Jo
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Patent number: 8026592Abstract: Through-Silicon-Via (TSV) structures can include a conductive via through a substrate extending from an upper surface of the substrate to a backside surface of the substrate opposite the upper surface, a conductive protective layer including Ni and/or Co can be at a bottom of the conductive via, and a separate polymer insulating layer can be on the backside surface of the substrate in contact with the conductive protective layer.Type: GrantFiled: March 20, 2009Date of Patent: September 27, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Minseung Yoon, Namseog Kim, Pyoungwan Kim, Keumhee Ma, Chajea Jo
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Publication number: 20100038800Abstract: Through-Silicon-Via (TSV) structures can include a conductive via through a substrate extending from an upper surface of the substrate to a backside surface of the substrate opposite the upper surface, a conductive protective layer including Ni and/or Co can be at a bottom of the conductive via, and a separate polymer insulating layer can be on the backside surface of the substrate in contact with the conductive protective layer.Type: ApplicationFiled: March 20, 2009Publication date: February 18, 2010Inventors: Minseung Yoon, Namseog Kim, Pyoungwan Kim, Keumhee Ma, Chajea Jo